PNX17XX Datasheet, PDF (183/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 5: The Clock Module
2.12.6 SPDO
xtal_clk
tst_clk
DDS5
GPIO
Figure 23: SPDO Clock
3. Registers Definition
BLOCKING
sel_clk_spdo
slice_tst_out
clk_spdo
3.1 Registers Summary
Table 10: Registers Summar
Offset
Name
0x04,7000
PLL0_CTL
0x04,7004
PLL1_CTL
0x04,7008
PLL2_CTL
0x04,700C
PLL1_7_CTL
0x04,7010
DDS0_CTL
0x04,7014
DDS1_CTL
0x04,718
DDS2_CTL
0x04,701C
DDS3_CTL
0x04,7020
DDS4_CTL
0x04,7024
DDS5_CTL
0x04,7028
DDS6_CTL
0x04,702C
DDS7_CTL
0x04,7030
DDS8_CTL
0x04,7034
CAB_DIV_PD
0x04,7038-
0x04,70FC
RESERVED
0x04,7100
CLK_TM_CTL
0x04,7104
CLK_MEM_CTL
0x04,7108
CLK_2D2_CTL
0x04,710C
CLK_PCI_CTL
0x04,7110
CLK_MBS_CTL
0x04,7114
CLK_TSTAMP_CTL
0x04,7118
CLK_LAN_CTL
0x04,711C
CLK_LAN_RX_CTL
0x04,7120
CLK_LAN_TX_CTL
Description
PLL0 Control Register
PLL1 Control Register
PLL2 Control Register
PLL 1.728 GHz Control Register
DDS0: frequency control
DDS1: frequency control
DDS2: frequency control
DDS3: frequency control
DDS4: frequency control
DDS5: frequency control
DDS6: frequency control
DDS7: frequency control
DDS8: frequency control
CAB Clocks divider powerdown signals
RESERVED
TM5250 clock control
DDR Memory clock control
2D Drawing engine clock control
PCI Clock control
MBS Clock control
Time Stamp Clock control
Ethernet Clock control
Ethernet RX Clock control
Ethernet TX Clock control
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
5-32