PNX17XX Datasheet, PDF (747/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 23: LAN100 — Ethernet Media Access Controller
Table 12: LAN100 Pin Interface to external PHY …Continued
Directio
Pin
n
Description
LAN_RX_ER
In
MII or RMII Receive Error
LAN_MDIO
In/Out MII Management data I/O
LAN_MDC
Out
MII Management Data clock
6.2 Power Management
The LAN100 supports power management by means of external clock switching.
Basically, all clocks in the LAN100 module can be switched off. If WoL is needed, the
receive clock should not be switched off.
The LAN100 supports two power management modes:
• Sleep mode: the PNX17xx Series is active while most clocks are switched off.
The CPU is active and can still communicate with the LAN100 via MMIO
registers.
• Coma mode: most of the clocks in the PNX17xx Series are switched off, including
the LAN100, CPU, and MMIO clock.
6.2.1 Sleep Mode
The LAN100 can be put in sleep mode by setting the PowerDown bit in the
PowerDown register if the receive and transmit DMA managers are disabled and
inactive. Clocks should only be disabled after software has set the PowerDown bit.
Software should prevent access to components of the LAN100 that have been
switched off. If an external PHY is connected, a WoL can still trigger an interrupt.
To enter sleep mode, software should:
• Disable both transmit DMA managers and the receive DMA manager by writing
the Command register
• Wait for the transmit and Receive Datapaths to be inactive by waiting for a
Finished interrupt or by polling the Status register.
• Set the PowerDown bit by writing to the PowerDown register.
If no PHY is connected software can directly set the PowerDown bit and disable the
clocks.
To exit sleep mode sofware should:
• Reset the PowerDown bit
• Reenable the receive and Transmit Datapaths.
6.2.2 Coma Mode
PNX17XX_SER_1
Preliminary data sheet
In coma mode, most of the clocks in the PNX17xx Series can be switched off
including the CPU and MMIO clocks. If an external PHY is connected, the receive
filter and WoL detection will still be active and capable of generating a WoL interrupt
to the system’s power-management controller.
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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