PNX17XX Datasheet, PDF (575/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 18: SPDIF Input
5. Register Descriptions
5.1 Register Summary
5.1.1 SPDIF Input Interrupt Registers
The registers SPDI_STATUS, SPDI_INTSET, SPDI_INTCLR and SPDI_INTEN
support DVP block level interrupt processing. The SPDIF Input interrupt control
mechanism is discussed in detail in section Section 3.2.11.
Address
offset:
31
27
23
0x000
SPDI_CTL (r/w)
0x004
0x008
0x00C
0x010
0x014
0x018
0x02C
0x030
0x044
SPDI_BASE1 (r/w)
SPDI_BASE2 (r/w)
SPDI_SIZE (r/w)
SPDI_BPTR (r/o)
SPDI_SMPMASK (r/w)
SPDI_CBITS1 (r/o)
6 registers total
SPDI_CBITS6 (r/o)
SPDI_UBITS1 (r/o)
6 registers total
SPDI_UBITS6 (r/o)
Figure 9: SPDIF Input MMIO Registers (1 of 2)
19
15
11
7
3
0
GL-FILTER[3:0]
UCBITS_SEL
CHAN_MODE[1:0]
SAMP_MODE[1:0]
DIAG_MODE
CAP_ENABLE
RESET
BASE1
BASE2
SIZE (in bytes)
ADDRESS
CBITS[31:0]
000000
000000
000000
SMASK
CBITS[191:159]
UBITS[31:0]
UBITS[191:159]
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
18-15