PNX17XX Datasheet, PDF (105/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 2: Overview
PNX17xx Series can act as PCI bus arbiter for up to 3 external masters, i.e. total of 4
masters with PNX17xx Series, without external logic.
PCI clock is an input to PNX17xx Series, but if desired the general purpose PNX17xx
Series PCI_SYS_CLK clock output can be used as the PCI 32 MHz clock for the
entire system.
Table 8 summarizes the PCI features supported by the PNX17xx Series.
Table 8: PNX17xx Series PCI capabilities
As PCI Target it responds to
As PCI master it initiates
IO Read
IO Write
Memory Read
Memory Read
Memory Write
Memory Write
Configuration Read
Configuration Read
Configuration Write
Configuration Write
Memory Read Multiple
Memory Read Multiple
Memory Read Line
Memory Read Line
Memory Write and Invalidate
Memory Write and Invalidate
Interrupt Acknowledge
10.3.2 Simple Peripheral Capabilities (‘XIO-8/16’)
The 16-bit micro-processor peripheral interface is a master-only interface, and
provides non-multiplexed address and data lines. A total of 26 address bits are
provided, as well as a bi-directional, 16-bit data bus. Five device profiles are provided,
each generating a chip-select for external devices. Up to 64 MB of address space is
allowed per device profile. The interface control signals are compatible with a
Motorola 68360 bus interface, and support both fixed wait-state or dynamic
completion acknowledgment.
A total of 5 pre-decoded Chip Select pins are available to accommodate typical
outside slave configurations with minimal or no external glue logic. Each chip select
pin has an associated programmable address range within the XIO address space.
Each chip select pin can also choose to obey external DTACK completion signalling,
or be set to have a pre-programmed number of wait cycles.
The peripheral interface derives 24 of the 26 address wires and 8 out of the 16 data
wires from the PCI AD[31:0] pins. The remaining pins are XIO specific and non PCI
shared. An ‘XIO’ access looks like a valid PCI transaction to PCI master/targets on
the same wires. Unused XIO pins are available as GPIO pins.
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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