PNX17XX Datasheet, PDF (655/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
2. Functional Description
2.1 VLD Block Level Diagram
VLD_INT
MMIO-DTL
Interface
Control and Status
Registers
start_code_detector
VLD State Machines
Shifter
Input DMA
dtl0
FIFO
mb_addr
mb_type
cbp
dmv and motion
dct_lum
dct_chr
dctcoef[0]
dctcoef[1]
escape_codes
Figure 1: VLD Block Diagram
3. Operation
Writeback
dtl1
Run Length
FIFO
Writeback
dtl2
MB Header
FIFO
3.1 Reset-Related Issues
A system reset will cause the Variable Length Decoder to clear all registers to default
values and will force all state machines to the IDLE state. Any DMA activity in
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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