PNX17XX Datasheet, PDF (303/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 8: General Purpose Input Output Pins
Table 10: Sampling and Pattern Generation Control Registers for the FIFO Queues
Bit Symbol
Acces
s
Value
Description
20:16 CARRIER_DIV
R/W 00
(when FIFO_MODE[1]
=1)
Used in Ir TX applications if a sub-carrier is required for
transmission. To enable this divider EN_IR_CARRIER=1.
If enabled, the Ir sub-carrier frequency is defined by programming
FREQ_DIV and the ‘ONTIME’ is defined by FREQ_DIV x
CARRIER_DIV.
0x00 - Disabled.
0x01 - Disabled.
0x02 - Sampling frequency is FREQ_DIV/2
.....
0x1F - Sampling frequency is FREQ_DIV/31
18:16
IR_FILTER
(when FIFO_MODE[1]
=0)
Used in Ir RX applications to filter a received Ir signal. To enable this
divider EN_IR_FILTER=1.
If enabled, Ir pulses greater than IR_FILTER are passed through to
00
the signal monitoring logic.
0x0 - 54/108 MHz, 0.5 µs
0x1 - 108/108 MHz, 1.0 µs
0x2 - 162/108 MHz, 1.5 µs
0x3 - 216/108 MHz, 2.0 µs
0x4 - 270/108 MHz, 2.5 µs
0x5 - 324/108 MHz, 3.0 µs
0x6 - 378/108 MHz, 3.5 µs
0x7 - 432/108 MHz, 4.0 µs
Note: The filter operates on one input per queue, this bit is the input
selected by IO_SEL[7:0]. If used in multi-bit sampling modes
(IO_SEL_EN = 01 or 10) be aware that the filtered signal is delayed
by the selected IR_FILTER value with respect to the other signals
sampled in the queue.
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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