PNX17XX Datasheet, PDF (733/832 Pages) NXP Semiconductors – Connected Media Processor

Philips Semiconductors
Volume 1 of 1
PNX17xx Series
Chapter 23: LAN100 — Ethernet Media Access Controller
When the flow control must last a long time, a sequence of pause frames must be
transmitted. This is supported with a mirror counter mechanism. To enable mirror
counting, write a non-zero value to the MirrorCounter[15:0] bits in the
FlowControlCounter register. When the TxFlowControl bit is asserted, a pause frame
is transmitted. After sending the pause frame, an internal mirror counter is initialized
to zero. The internal mirror counter starts incrementing once every 512 bit-slot times.
When the internal mirror counter reaches the MirrorCounter value, another pause
frame is transmitted with a pause-timer value equal to the PauseTimer field from the
FlowControlCounter register. The internal mirror counter is reset to zero and the
counter restarts.
The register MirrorCounter[15:0] is usually set to a smaller value than the
PauseTimer[15:0] register to ensure an early expiration of the mirror counter so as to
be able to send a new pause frame before the transmission on the other side can
resume. By continuing to send pause frames before the transmitting side finishes
counting the pause timer, the pause can be extended as long as TxFlowControl is
asserted. This continues until TxFlowControl is deasserted, when a final pause frame
with a pause-timer value of 0x0000 is automatically sent to abort flow control and
resume transmission.
To disable the mirror counter mechanism, write the value 0 to MirrorCounter field in
the FlowControlCounter register. When using the mirror counter mechanism to
account for time-of-flight delays, frame transmission time, queuing delays, crystal
frequency tolerances, and response time delays, the MirrorCounter should be
programmed conservatively, typically at about 80% of the PauseTimer value.
If the software device driver sets the MirrorCounter field of the FlowControlCounter
register to zero, the LAN100 will only send one pause control frame. After sending the
pause frame, an internal pause counter is initialized to zero; the internal pause
counter is incremented by one every 512 bit-slot times. Once the internal pause
counter reaches the value of the PauseTimer register, the LAN100 will reset the
TxFlowControl bit in the Command register. The software device driver can poll the
TxFlowControl bit to detect when the pause completes.
The value of the internal counter in the flow-control module can be read out via the
FlowControlStatus register. If the MirrorCounter is non-zero, the FlowControlStatus
register will return the value of the internal mirror counter; if the MirrorCounter is zero,
the FlowControlStatus register will return the value of the internal pause counter
value.
The device driver may dynamically modify the MirrorCounter register value and
switch between zero MirrorCounter and non-zero-valued MirrorCounter modes.
Transmit flow control is enabled via the TX_FLOW_CONTROL bit in the MAC1
configuration register. If the TX_FLOW_CONTROL bit is zero, then the MAC will not
transmit pause control frames, and software must not initiate pause frame
transmissions, and the TxFlowControl bit in the Command register should be zero.
PNX17XX_SER_1
Preliminary data sheet
Rev. 1 — 17 March 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
23-60