OX16PCI954_05 Datasheet, PDF (9/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
4 PIN DESCRIPTIONS
Mode
00
01
10
11
PCI interface
139, 140, 141, 143, 144, 145, 148,
149, 152, 154, 155, 156, 159, 160,
1, 2, 14, 15, 16, 19, 20, 23, 24, 26,
28, 29, 32, 33, 34, 36, 37, 38
150, 3, 13, 27
136
4
7
5
6
9
12
11
10
151
134
132,133
138
Serial port pins
46
N/A
Dir¹
P_I/O
P_I
P_I
P_I
P_O
P_I
P_O
P_O
P_I/O
P_O
P_I/O
P_I
P_I
P_OD
P_OD
I
Name
AD[31:0]
C/BE[3:0]#
CLK
FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
PAR
SERR#
PERR#
IDSEL
RST#
INTA#, INTB#
PME#
FIFOSEL
80, 79, 55, 54
N/A O SOUT[3:0]
Description
Multiplexed PCI Address/Data bus
PCI Command/Byte enable
PCI system clock
Cycle Frame
Device Select
Initiator ready
Target ready
Target Stop request
Parity
System error
Parity error
Initialization device select
PCI system reset
PCI interrupts
Power management event
FIFO select. For backward compatibility with 16C550,
16C650 and 16C750 devices the UARTs’ FIFO depth is 16
when FIFOSEL is low. The FIFO size is increased to 128
when FIFOSEL is high. The unlatched state of this pin is
readable by software. The FIFO size may also be set to 128
by setting FCR[5] when LCR[7] is set, or by putting the
device into enhanced mode.
UART serial data outputs
87, 69, 68, 47
IrDA_Out[3:0] UART IrDA data output when MCR[6] of the corresponding
channel is set in enhanced mode
N/A
I SIN[3:0]
UART serial data inputs
85, 74, 66, 49
82, 77, 59, 52
I IrDA_In[3:0]
UART IrDA data input when IrDA mode is enabled (see
above)
N/A
I DCD[3:0]#
Active-low modem data-carrier-detect input
N/A O DTR[3:0]#
Active-low modem data-terminal-ready output. If automated
DTR# flow control is enabled, the DTR# pin is asserted and
deasserted if the receiver FIFO reaches or falls below the
programmed thresholds, respectively.
O 485_En[3:0]
In RS485 half-duplex mode, the DTR# pin may be
programmed to reflect the state of the the transmitter empty
bit to automatically control the direction of the RS485
transceiver buffer (see register ACR[4:3])
O Tx_Clk_Out[3:0] Transmitter 1x clock (baud rate generator output). For
isochronous applications, the 1x (or Nx) transmitter clock
may be asserted on the DTR# pins (see register CKS[5:4])
DS-0029 Jul 05
External—Free Release
Page 9