OX16PCI954_05 Datasheet, PDF (34/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
Register SPR R/W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Offset ¹⁰
Indexed Control Register Set
ACR
0x00
R/W Addit-
ICR
950
DTR definition and
Auto
Tx
Rx
ional
Read Trigger
control
DSR Disable Disable
Status Enable Level
Flow
Enable
Enable
Control
Enable
CPR
0x01
R/W
5 Bit “integer” part of
3 Bit “fractional” part of
clock prescaler
clock prescaler
TCR
0x02
R/W
Unused
4 Bit N-times clock
selection bits [3:0]
CKS
0x03
R/W Tx 1x Tx CLK BDOUT DTR 1x Rx 1x
0
Receiver
Mode Select on DTR Tx CLK Mode
Clock Sel[1:0]
TTL
0x04
R/W Unused
Transmitter Interrupt Trigger Level (0-127)
RTL
0x05
R/W Unused
Receiver Interrupt Trigger Level (1-127)
FCL
0x06
R/W Unused
Automatic Flow Control Lower Trigger Level (0-127)
FCH
0x07
R/W Unused
ID1
0x08
R
ID2
0x09
R
ID3
0x0A
R
Automatic Flow Control Higher Trigger level (1-127)
Hardwired ID byte 1 (0x16)
Hardwired ID byte 1 (0xC9)
Hardwired ID byte 1 (0x50)
REV
0x0B
R
Hardwired revision byte (0x01)
CSR
NMR
MDM
RFC
GDS
0x0C
0x0D
0x0E
0X0F
0X10
W
Writing 0x00 to this register will
reset the UART (Except the CKS register)
R/W
Unused
9^th Bit
9^th Bit
9^th Bit
9^th Bit 9^th-bit Int. 9 Bit
SChar 4 SChar 3 SChar 2 SChar 1
En.
Enable
R/W
0
0
SIN
Modem Δ DCD Trailing Δ DSR Δ CTS
wakeup Wakeup Wakeup RI edge Wakeup Wakeup
disable Disable disable disable disable disable
R FCR[7] FCR[6] FCR[5] FCR[4] FCR[3] FCR[2] FCR[1] FCR[0]
R
0
0
0
0
0
0
0
Good
data
status
Table 17: Indexed Control Register Set
Note 10: The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the Indexed Control Registers via ICR.
Offset values not listed in the table are reserved for future use and must not be used.
To read or write to any of the Indexed Controlled Registers use the following procedure:
Writing to ICR registers:
Ensure that the last value written to LCR was not 0xBF (reserved for 650 compatible register access value).
Write the desired offset to SPR (address 111b).
Write the desired value to ICR (address 101b).
Reading from ICR registers:
Ensure that the last value written to LCR was not 0xBF (see above).
Write 0x00 offset to SPR to select ACR.
Set bit 6 of ACR (ICR read enable) by writing x1xxxxxxb to address 101b. Ensure that other bits in ACR are not changed.
(Software drivers should keep a copy of the contents of the ACR elsewhere since reading ICR involves overwriting ACR!)
Write the desired offset to SPR (address 111b).
Read the desired value from ICR (address 101b).
Write 0x00 offset to SPR to select ACR.
Clear bit 6 of ACR bye writing x0xxxxxxb to ICR, thus enabling access to standard registers again.
DS-0029 Jul 05
External—Free Release
Page 34