OX16PCI954_05 Datasheet, PDF (32/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
7.2 Register description tables
Each UART is accessed through an 8-byte block of I/O space (or through memory space). Since there are more than 8 registers,
the mapping is also dependent on the state of the Line Control Register ‘LCR’ and Additional Control Register ‘ACR’:
1. LCR[7]=1 enables the divider latch registers DLL and DLM.
2. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables
access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection.
3. ACR[7]=1 enables access to the 950 specific registers.
4. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 34.
Register Address R/W
Name
THR ¹
000
W
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2
Data to be transmitted
Bit 1
Bit 0
RHR ¹
000
R
Data received
IER ^1,2
CTS
RTS Special
650/950
Mode
550/750
Mode
001
interrupt interrupt Char.
R/W ^mask
mask Detect
Alternate
Sleep
mode
Modem
interrupt
mask
Rx Stat
interrupt
mask
THRE
interrupt
mask
RxRDY
interrupt
mask
Unused
sleep
mode
FCR ³
RHR Trigger
THR Trigger
650 mode
750 mode
010
W
Level
RHR Trigger
Level
Level
FIFO
Size
Unused
Tx
Trigger
Enable
Flush
THR
Flush
RHR
Enable
FIFO
950 mode
Unused
ISR ³
010
R
FIFOs
enabled
Interrupt priority
(Enhanced mode)
Interrupt priority
(All modes)
Interrupt
pending
LCR ⁴
011
Divisor
R/W latch
access
Tx
break
Force
parity
Odd /
even
parity
Parity
enable
Number
of stop
bits
Data length
MCR ^3,4
550/750
Mode
650/950
Mode
CTS &
100
R/W
Unused
RTS
Flow
Control
Enable
Internal
Loop
Baud
prescale
IrDA
mode
XON-Any
Back
Unused
RTS
DTR
LSR ^3,5
Normal
101
9-bit data
mode
MSR ³
110
Data
Error
Tx Empty
THR
Empty
Rx
Break
Framing
Error
Parity
Error
Overrun
Error
RxRDY
R
9^th Rx
data bit
R
DCD
RI
DSR
CTS
Delta Trailing Delta
Delta
DCD RI edge DSR
CTS
SPR ³
Normal
111
R/W
9-bit data
mode
Temporary data storage register and
Indexed control register offset value bits
Unused
9^th Tx
data bit
Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1.
DLL
000
R/W
Divisor latch bits [7:0] (Least significant byte)
DLM
001
R/W
Divisor latch bits [15:8] (Most significant byte)
Table 14: Standard 550 Compatible Registers
DS-0029 Jul 05
External—Free Release
Page 32