OX16PCI954_05 Datasheet, PDF (25/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
6.4.7 UART Interrupt Source Register ‘UIS’ (Offset 0x18)
The UART Interrupt Source register is described below:
Bits
5:0
11:6
17:12
23:18
26:24
27
28
29
30
31
Description
Read/Write
EEPROM
PCI
UART0 Interrupt Source Register (ISR[5:0])
-
R
UART1 Interrupt Source Register (ISR[5:0])
-
R
UART2 Interrupt Source Register (ISR[5:0])
-
R
UART3 Interrupt Source Register (ISR[5:0])
-
R
Reserved
-
R
UART0 Good-Data Status
-
R
UART1 Good-Data Status
-
R
UART2 Good-Data Status
-
R
UART3 Good-Data Status
-
R
Global Good-Data Status. This bit is the logical AND of bits 27 to 30, i.e.
-
R
it is set if Good-Data Status of all internal UARTs is set.
Reset
01h
01h
01h
01h
00h
1
1
1
1
1
Good-Data status for a given internal UART is set when all of the following conditions are met:
• ISR reads a level0 (no-interrupt pending), a level 2a (receiver data available, a level 2b (receiver time-out) or a level 3
(transmitter THR empty) interrupt
• LSR[7] is clear so there is no parity error, framing error or break in the FIFO
• LSR[1] is clear so no over-run error has occurred
If the device driver software reads the receiver FIFO levels (URL) followed by this register, then if Good-Data status for a given
channel is set, the driver can remove the number of bytes indicated by the FIFO level without the need to read the line status
register for that channel. This feature enhances the driver efficiency.
For a given channel, if the Good-Data status bit is not set, then the software driver should examine the corresponding ISR bits.
For example if bit 29 is low, then the driver should examine bits 17 down to 12 to obtain the ISR[5:0] for UART2. If the ISR
indicates a level 4 or higher interrupt, the interrupt is due to a change in the state of modem lines or detection of flow control
characters. The device driver-software should then take appropriate measures as would in any other 550/950 driver. When ISR
indicates a level 1 (receiver status) interrupt then the driver can examine the Line Status Register (LSR) of the relevant channel.
Since reading the LSR clears LSR[7], the device driver-software should either flush or empty the contents of the receiver FIFO,
otherwise the Good-Data status will no longer be valid.
The UART Receiver FIFO Level (URL), UART Transmitter FIFO Level (UTL), UART Interrupt Source register (UIS) and Global
Interrupt Status register (GIS) are allocated adjacent address offsets (10h to 1Ch) in the Base Address Register. The device
driver-software can read all of the above registers in single burst read operation. The location offset of the registers are such that
the FIFO levels are usually read before the status registers so that the status of the N characters indicated in the receiver FIFO
levels are valid.
DS-0029 Jul 05
External—Free Release
Page 25