OX16PCI954_05 Datasheet, PDF (48/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
ASR[5]: FIFOSEL
This bit reflects the unlatched state of the FIFOSEL pin.
ASR[6]: FIFO size
logic 0 ⇒FIFOs are 16 deep if FCR[0] = 1.
logic 1 ⇒FIFOs are 128 deep if FCR[0] = 1.
ASR[7]: Transmitter Idle
logic 0 ⇒Transmitter is transmitting.
logic 1 ⇒Transmitter is idle.
This bit reflects the state of the internal transmitter. It is set
when both the transmitter FIFO and shift register are
empty.
7.11.2 FIFO Fill levels ‘TFL & RFL’
The number of characters stored in the THR and RHR can
be determined by reading the TFL and RFL registers
respectively. When data transfer is in constant operation,
the values should be interpreted as follows:
1. The number of characters in the THR is no greater
than the value read back from TFL.
2. The number of characters in the RHR is no less than
the value read back from RFL.
7.11.3 Additional Control Register ‘ACR’
The ACR register is located at offset 0x00 of the ICR
ACR[0]: Receiver disable
logic 0 ⇒ The receiver is enabled, receiving data and
storing it in the RHR.
logic 1 ⇒ The receiver is disabled. The receiver
continues to operate as normal to maintain the
framing synchronisation with the receive data
stream but received data is not stored into the
RHR. In-band flow control characters continue
to be detected and acted upon. Special
characters will not be detected.
Changes to this bit will only be recognised following the
completion of any data reception pending.
ACR[1]: Transmitter disable
logic 0 ⇒ The transmitter is enabled, transmitting any
data in the THR.
logic 1 ⇒ The transmitter is disabled. Any data in the
THR is not transmitted but is held. However, in-
band flow control characters may still be
transmitted.
Changes to this bit will only be recognised following the
completion of any data transmission pending.
ACR[2]: Enable automatic DSR flow control
logic 0 ⇒ Normal. The state of the DSR# line does not
affect the flow control.
logic 1 ⇒ Data transmission is prevented whenever the
DSR# pin is held inactive high.
This bit provides another automatic out-of-band flow control
facility using the DSR# line.
ACR[4:3]: DTR# line configuration
When bits 4 or 5 of CKS (offset 0x03 of ICR) are set, the
transmitter 1x clock or the output of the baud rate
generator (Nx clock) are asserted on the DTR# pin,
otherwise the DTR# pin is defined as follows:
logic [00] ⇒ DTR# is compatible with 16C450, 16C550,
16C650 and 16C750 (i.e. normal).
logic [01] ⇒ DTR# pin is used for out-of-band flow control.
It will be forced inactive high if the Receiver
FIFO Level (‘RFL’) reaches the upper flow
control threshold. DTR# line will be re-
activated (=0) when the RFL drops below the
lower threshold (see FCL & FCH).
logic [10] ⇒ DTR# pin is configured to drive the active-low
enable pin of an external RS485 buffer. In
this configuration the DTR# pin will be forced
low whenever the transmitter is not empty
(LSR[6]=0), otherwise DTR# pin is high.
logic [11] ⇒ DTR# pin is configured to drive the active-
high enable pin of an external RS485 buffer.
In this configuration, the DTR# pin will be
forced high whenever the transmitter is not
empty (LSR[6]=0), otherwise DTR# pin is low.
If the user sets ACR[4], then the DTR# line is controlled by
the status of the transmitter empty bit of LCR. When
ACR[4] is set, ACR[3] is used to select active high or active
low enable signals. In half-duplex systems using RS485
protocol, this facility enables the DTR# line to directly
control the enable signal of external 3-state line driver
buffers. When the transmitter is empty the DTR# would go
inactive once the SOUT line returns to it’s idle marking
state.
ACR[5]: 950 mode trigger levels enable
logic 0 ⇒ Interrupts and flow control trigger levels are as
described in FCR register and are compatible
with 16C650/16C750 modes.
logic 1 ⇒ 16C950 specific enhanced interrupt and flow
control trigger levels defined by RTL, TTL, FCL
and FCH are enabled.
ACR[6]: ICR read enable
logic 0 ⇒ The Line Status Register is readable.
logic 1 ⇒ The Indexed Control Registers are readable.
Setting this bit will map the ICR set to the LSR location for
reads. During normal operation this bit should be cleared.
DS-0029 Jul 05
External—Free Release
Page 48