OX16PCI954_05 Datasheet, PDF (59/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
10.2.3 Zone2: Identification Registers
The Zone2 region of EEPROM contains the program value
for Vendor ID and Subsystem Vendor ID. The format of
Device Identification configuration WORDs are described in
Table 34.
Bits Description
15 ‘0’ = There are no more Zone2 (Identification)
bytes to program. Move to the next available
zone or end EEPROM program if no more zones
are enabled in the Header.
‘1’ = There is another Zone2 (Identification) byte
to follow.
14:8 0x00 = Vendor ID bits [7:0].
0x01 = Vendor ID bits [15:8].
0x02 = Subsystem Vendor ID [7:0].
0x03 = Subsystem Vendor ID [15:8].
0x03 to 0x7F = Reserved.
7:0 8-bit value of the register to be programmed
Table 34: Zone 2 data format
10.2.4 Zone3: PCI Configuration Registers
The Zone3 region of EEPROM contains any changes
required to the PCI Configuration registers (with the
exception of Vendor ID and Subsystem Vendor ID which
are programmed in Zone2). This zone is divided into two
groups, each of which consists of a function header
WORD, and one or more configuration WORDs for that
function. The function header is described in Table 35.
Bits Description
15 ‘0’ = End of Zone 3.
‘1’ = Define this function header.
14:3 Reserved. Write zeros.
2:0 Function number for the following configuration
WORD(s).
‘000’ = Function0 (Internal UARTs)
‘001’ = Function1 (Local Bus / Parallel Port)
Other values = Reserved.
Table 35: Zone 3 data format (Function Header)
The subsequent WORDs for each function contain the
address offset and a byte of programming data for the PCI
Configuration Space belonging to the function number
selected by the proceeding Function-Header. The format of
configuration WORDs for the PCI Configuration Registers
are described below.
Bits Description
15 ‘0’ = This is the last configuration WORD in for
the selected function in the Function-Header.
‘1’ = There is another WORD to follow for this
function.
14:8 These seven bits define the byte-offset of the PCI
configuration register to be programmed. For
example the byte-offset of the Interrupt Pin
register is 0x3D. Offset values are tabulated in
section 6.2.
7:0 8-bit value of the register to be programmed
Table 36: Zone 3 data format (data)
Table 37 shows which PCI Configuration registers are
writable from the EEPROM for each function.
Offset Bits Description
0x02 7:0 Device ID bits 7 to 0.
0x03 7:0 Device ID bits 15 to 8.
0x06 3:0 Must be ‘0000’.
0x06 4 Extended Capabilities.
0x06 7:5 Must be ‘000’.
0x09 7:0 Class Code bits 7 to 0.
0x0A 7:0 Class Code bits 15 to 8.
0x0B 7:0 Class Code bits 23 to 16.
0x2E 7:0 Subsystem ID bits 7 to 0.
0x2F 7:0 Subsystem ID bits 15 to 8.
0x3D 7:0 Interrupt pin.
0x42 7:0 Power Management Capabilities
bits 7 to 0.
0x43 7:0 Power Management Capabilities
bits 15 to 8.
Table 37: EEPROM-writable PCI configuration registers
DS-0029 Jul 05
External—Free Release
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