OX16PCI954_05 Datasheet, PDF (42/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
750 (normal) mode:
logic 0 ⇒ CTS/RTS flow control disabled.
logic 1 ⇒ CTS/RTS flow control enabled.
In non-enhanced mode, this bit enables the CTS/RTS out-
of-band flow control.
MCR[6]: IrDA mode
logic 0 ⇒ Standard serial receiver and transmitter data
format.
logic 1 ⇒ Data will be transmitted and received in IrDA
format.
This function is only available in Enhanced mode. It
requires a 16x clock to function correctly.
MCR[7]: Baud rate prescaler select
logic 0 ⇒ Normal (divide by 1) baud rate generator
prescaler selected.
logic 1 ⇒ Divide-by-“M+N/8” baud rate generator
prescaler selected.
where M & N are programmed in CPR (ICR offset 0x01).
After a hardware reset, CPR defaults to 0x20 (divide-by-4)
and MCR[7] is reset. User writes to this flag will only take
effect in Enhanced mode. See section 7.9.1.
7.8 Other Standard Registers
7.8.1 Divisor Latch Registers ‘DLL & DLM’
The divisor latch registers are used to program the baud
rate divisor. This is a value between 1 and 65535 by which
the input clock is divided by in order to generate serial
baud rates. After a hardware reset, the baud rate used by
the transmitter and receiver is given by:
Baudrate = ^InputClock
16 * Divisor
Where divisor is given by DLL + ( 256 x DLM ). More
flexible baud rate generation options are also available.
See section 7.10 for full details.
OX16PCI954
7.7.2 Modem Status Register ‘MSR’
MSR[0]: Delta CTS#
Indicates that the CTS# input has changed since the last
time the MSR was read.
MSR[1]: Delta DSR#
Indicates that the DSR# input has changed since the last
time the MSR was read.
MSR[2]: Trailing edge RI#
Indicates that the RI# input has changed from low to high
since the last time the MSR was read.
MSR[3]: Delta DCD#
Indicates that the DCD# input has changed since the last
time the MSR was read.
MSR[4]: CTS
This bit is the complement of the CTS# input. It is
equivalent to RTS (MCR[1]) in internal loop-back mode.
MSR[5]: DSR
This bit is the complement of the DSR# input. It is
equivalent to DTR (MCR[0]) in internal loop-back mode.
MSR[6]: RI
This bit is the complement of the RI# input. In internal loop-
back mode it is equivalent to the internal OUT1.
MSR[7]: DCD
This bit is the complement of the DCD# input. In internal
loop-back mode it is equivalent to the internal OUT2.
7.8.2 Scratch Pad Register ‘SPR’
The scratch pad register does not affect operation of the
rest of the UART in any way and can be used for
temporary data storage. The register may also be used to
define an offset value to access the registers in the
Indexed Control Register set. For more information on
Indexed Control registers see sections 7.2 and 7.11.
DS-0029 Jul 05
External—Free Release
Page 42