OX16PCI954_05 Datasheet, PDF (28/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
6.6 Power Management
The OX16PCI954 is compliant with PCI Power
Management Specification Revision 1.0. Each logical
function implements its own set of Power Management
registers and supports the power states D0, D2 and D3.
Power management is accomplished by power-down and
power-up requests, asserted via interrupts and the PME#
pin respectively. Each function can assert the PME# pin
independently. The PME# pin is de-asserted when the
sticky PME_Status bit is cleared in both functions.
Power-down request is not defined by Power Management
1.0. It is a device-specific feature and requires a bespoke
device driver implementation. The device driver can either
implement the power-down itself or in the case of Function
0, use a special interrupt and power-down features offered
by the device to determine when the UARTs are ready for
power-down.
The PME# pin can, in certain cases, activate the PME#
signal when power is removed from the device, which will
cause the PC to wake up from Low-power state D3(cold).
To ensure full cross-compatibility with systemboard
implementations, use of an isolator FET is recommended.
If Power Management capabilities are not required, the
PME# pin can be treated as no-connect.
6.6.1 Power Management of Function 0
Function 0 can be configured to monitor the activity of the
serial channels, and issue a power-down interrupt when all
four ports are inactive (no interrupts pending and both
transmitter and receiver are idle). It can also issue a wake-
up request on the PME# line from power states D2 and D3.
The conditions for inactive mode are the same as the ones
for sleep-mode (see section 7.6.4); however power
management operation and 16C950 sleep mode are
separate and independent operations, affording maximum
flexibility in power usage.
Whenever the device driver places Function0 in power-
state D3, the clock to all internal UARTs is shut off
immediately and will only be turned on when the device
driver places function0 in power-state D0. In this case, only
activity on the RI line (the trailing edge of a pulse) will
assert a wake-up request. Wake-up from power sate D2 is
configurable, and can be triggered by activity on any
combination of modem lines or the serial data input (SIN)
line. See section 7.11.10 to mask wakeup events. In case
of a wake up request from SIN when function0 is in power-
state D2, the clock for that channel is turned on so serial
data framing can be maintained.
When all channels are ready for power-down (i.e. inactive),
the power management circuitry waits for a period of time
programmed in Power-down Filter Time (LCC[6:5], see
section 6.4.1) and if all channels are still inactive, the
OX16PCI954 can issue a PCI interrupt if it is enabled. The
filter stops the UARTs from issuing too many interrupts
whenever the UART activity is intermittent. Upon a power
down interrupt, the device driver can change the power-
state of Function0 as required. Note that the power-state of
the device is only changed by the device driver and at no
point will the OX16PCI954 change its own power state.
The interrupt merely informs the device driver that this PCI
logical function can is ready for power down.
When enabled, the power-down interrupt status is reflected
in GIS[5] which is normally used to return the value of
MIO1. It also uses the corresponding interrupt mask bit,
GIS[21]. The interrupt masking operation is shown in Table
11.
The device driver can enable the power-down request by
first writing a power-down filter time to LCC[6:5] which is
not ‘00’. Then it can either operate in polling mode by
reading GIS[5] or use a PCI interrupt. When LCC[6:5] is not
‘00’, GIS[5] will be a ‘sticky-bit’ which is set whenever there
is power-down request from Function 0. This bit is cleared
when the device driver reads the GIS[5] register. GIS[5] will
assert a PCI interrupt if GIS[21] is set.
Function0 implements the PCI Power Management power-
states D0, D2 and D3. Whenever the device driver
changes the power-state to state D2 or D3, Function0
takes the following actions:
• The internal clock to internal UARTs is shut down.
• PCI interrupt for Function0 is disabled regardless of
the value of GIS[19:16].
• Access to I/O or Memory BARs of Function0 is
disabled.
However, access to the configuration space is still enabled.
Function0 can issue a wake up request by asserting PME#
if it is enabled by PMCSR[8] of Function0. The PME#
assertion is immediate and does not use the power-down
filter timer. It operates even if LCC[6:5] is set to ‘00’. The
wake up condition for Function0 is as follows:-
When Function0 is in power-state D3, a trailing edge on the
modem line ‘RI’ asserts PME# as long PMCSR[8] is set.
When Function0 is in power-state D3, a change in the state
of any modem line which is enabled by a 16C950-specific
mask bit, or a change in the state of the serial input line if
enabled by a 16C950-specific mask bit can issue a wake
up request by asserting the PME# signal (see section
8.4.11). After a hardware reset all of these mask bits are
cleared to enable wake up PME# assertion from all modem
lines and the SIN line. As the wake up operation requires at
least one mask bit to be enabled, the device driver can for
example disable the masks from three UART channels so
that only one channel can issue a wake up request, or
DS-0029 Jul 05
External—Free Release
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