OX16PCI954_05 Datasheet, PDF (17/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
6.3 Accessing logical functions
Access to the UARTs, local bus and parallel port is achieved via standard I/O and memory mapping, at addresses defined by the
Base Address Registers (BARs) in configuration space. The BARs are configured by the system to allocate blocks of I/O and
memory space to the logical functions, according to the size required by the function. The addresses allocated can then be used
to access the functions. The mapping of these BARs is shown inTable 6.
BAR
Function 0
Function 1
Local bus
Parallel port
0
Internal UARTs (I/O mapped) Local bus (I/O mapped)
Parallel port base registers
1 Internal UARTs (memory mapped) Local bus (memory mapped)
Parallel port extended registers
2
Local configuration registers (I/O mapped)
3
Local configuration registers (memory mapped)
4
Unused
5
Unused
Table 6: Base Address Register definition
6.3.1 PCI access to internal UARTs
IO and memory space
BAR 0 and BAR 1 of function 0 are used to access the
internal UARTs. The function reserves a 32-byte block of
I/O space and a 4K byte block of memory space. Once the
I/O access enable and Memory access enable bits in the
Command register (configuration space) are set, the
UARTs can be accessed following the mapping shown in
Table 7.
UART
Address
(hex)
000
001
002
003
004
005
006
007
UART
Address
000
001
002
003
004
005
006
007
PCI Offset from Base Address 0 for
Function0 in IO space (hex)
UART0 UART1 UART2 UART3
00
08
10
18
01
09
11
19
02
0A
12
1A
03
0B
13
1B
04
0C
14
1C
05
0D
15
1D
06
0E
16
1E
07
0F
17
1F
PCI Offset from Base Address 1 for
Function0 in Memory space (hex)
00
20
40
60
04
24
44
64
08
28
48
68
0C
2C
4C
6C
10
30
50
70
14
34
54
74
18
38
58
78
1C
3C
5C
7C
Table 7: PCI address map for internal UARTs
(I/O and memory)
Note 1:
Since 4K of memory space is reserved and the full bus
address is not used for decoding, there are a number of
aliases of the UARTs in the allocated memory region
6.3.2 PCI access to 8-bit local bus
When the local bus is enabled (Mode 00), access to the
bus works in similar fashion to the internal UARTs. The
function reserves a block of I/O space and a block of
memory space. The I/O block size is user definable in the
range of 4 to 256 bytes; the memory range is fixed at 4K
bytes.
I/O space
In order to minimise the usage of IO space, the block size
for BAR0 of Function1 is user definable in the range of 4 to
256 bytes. Having assigned the address range, the user
can define two adjacent address bits to decode up to four
chip selects internally. This facility allows glueless
implementation of the local bus connecting to four external
peripheral chips. The address range and the lower address
bit for chip-select decoding (Lower-Address-CS-Decode)
are defined in the Local Bus Configuration register (see
LT2[26:20] in section 6.4).
The 8-bit Local Bus has eight address lines (LBA[7:0])
which correspond to the maximum IO address space. If the
maximum allowable block size is allocated to the IO space
(i.e. 256 bytes), then as access in IO space is byte aligned,
LBA[7:0] equal PCI AD[7:0] respectively. When the user
selects an address range which is less than 256 bytes, the
corresponding upper address lines will be set to logic zero.
The region can be divided into four chip-select regions
when the user selects the second uppermost non-zero
address bit for chip-select decoding. For example if 32-
bytes of IO space are reserved, the local bus address lines
A[4:0] are active and the remaining address lines are set to
zero. To generate four chip-selects the user should select
A3 as the Lower-Address-CS-Decode. In this case A[4:3]
will be used internally to decode chip-selects, asserting
LBCS0# when the address offset is 00-07h, LBCS1# when
DS-0029 Jul 05
External—Free Release
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