OX16PCI954_05 Datasheet, PDF(63/73 Page) Oxford Semiconductor – Integrated Quad UART and PCI interface

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OX16PCI954_05 Datasheet, PDF (63/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

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OXFORD SEMICONDUCTOR LTD.

OX16PCI954

Symbol

tref

tza

tads

tzrds1

tzrds2

vtdrd

tzd1

tzd2

tsd

thd

Parameter

IRDY# falling to reference LBCLK

Reference LBCLK to Address Valid

Address Valid to LBDS# falling

Reference LBCLK to LBDS# falling

Reference LBCLK to LBDS# rising

Data bus floating to LBDS# falling

Reference LBCLK to data bus floating at the start of the read

transaction

Reference LBCLK to data bus driven by OX16PCI954 at the end of the

read transaction

Data bus valid to LBDS# rising

Data bus valid after LBDS# rising

Min

Max

Units

Nominally 2 PCI clock cycles

TBD

Table 44: Read operation from Motorola-type Local Bus

Symbol

tref

tza

tads

tzw1

tzw2

twds

tdsw

tzwds1

tzwds2

tzdv

tzdf

tdsdi

Parameter

IRDY# falling to reference LBCLK

Reference LBCLK to Address Valid

Address Valid to LBDS# falling

Reference LBCLK to LBRDWR# falling

Reference LBCLK to LBRDWR# rising

LBRDWR# falling to LBDS# falling

LBDS# rising to LBRDWR# rising

Reference LBCLK to LBDS# falling

Reference LBCLK to LBDS# rising

Reference LBCLK to data bus valid

Reference LBCLK to data bus high-impedance

LBDS# rising to data bus invalid

Min

Max

Units

Nominally 2 PCI clock cycles

TBD

Table 45: Write operation to Motorola-type Local Bus

13.3 Serial ports

Isochronous (x1 Clock) Timing:

Symbol

tirs

tirh

tits

Parameter

SIN set-up time to Isochronous input clock âRx_Clk_In rising 1

SIN hold time after Isochronous input clock âRx_Clk_Inâ rising 1

SOUT valid after Isochronous output clock âTx_Clk_Outâ falling 1

Min

Max

Units

TBD

Table 46: Isochronous mode timing

Note 1:

In Isochronous mode, transmitter data is available after the falling edge of the x1 clock and the receiver data is sampled using the rising edge of the

x1 clock. The system designer is should ensure that mark-to-space ratio of the x1 clock is such that the required set-up and hold timing constraint

are met. One way of achieving this is to choose a crystal frequency which is twice the required data rate and then divide the clock by two using the

on-board prescaler. In this case the mark-to-space ratio is 50/50 for the purpose of set-up and hold calculations.

DS-0029 Jul 05

ExternalâFree Release

Page 63

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