OX16PCI954_05 Datasheet, PDF(36/73 Page) Oxford Semiconductor – Integrated Quad UART and PCI interface

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OX16PCI954_05 Datasheet, PDF (36/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

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OXFORD SEMICONDUCTOR LTD.

OX16PCI954

7.4 Transmitter and receiver FIFOs

Both the transmitter and receiver have associated holding

registers (FIFOs), referred to as the transmitter holding

respectively.

In normal operation, when the transmitter finishes

transmitting a byte it will remove the next data from the top

of the THR and proceed to transmit it. If the THR is empty,

it will wait until data is written into it. If THR is empty and

the last character being transmitted has been completed

(i.e. the transmitter shift register is empty) the transmitter is

said to be idle. Similarly, when the receiver finishes

receiving a byte, it will transfer it to the bottom of the RHR.

If the RHR is full, an overrun condition will occur (see

section 7.5.3).

Data is written into the bottom of the THR queue and read

from the top of the RHR queue completely asynchronously

to the operation of the transmitter and receiver.

The size of the FIFOs is dependent on the setting of the

FCR register. When in Byte mode, these FIFOs only

accept one byte at a time before indicating that they are

full; this is compatible with the 16C450. When in a FIFO

mode, the size of the FIFOs is either 16 (compatible with

the 16C550) or 128.

Data written to the THR when it is full is lost. Data read

from the RHR when it is empty is invalid. The empty or full

status of the FIFOs are indicated in the Line Status

when the UART is ready for data transfer to/from the

FIFOs. The number of items in each FIFO may also be

read back from the transmitter FIFO level (TFL) and

receiver FIFO level (RFL) registers (see section 7.11.2).

7.4.1 FIFO Control Register âFCRâ

FIFO setup:

FCR[0]: Enable FIFO mode

logic 0 âByte mode.

logic 1 âFIFO mode.

This bit should be enabled before setting the FIFO trigger

levels.

FCR[1]: Flush RHR

logic 0 âNo change.

logic 1 âFlushes the contents of the RHR

This is only operative when already in a FIFO mode. The

RHR is automatically flushed whenever changing between

Byte mode and a FIFO mode. This bit will return to zero

after clearing the FIFOs.

FCR[2]: Flush THR

logic 0 â No change.

logic 1 âFlushes the contents of the THR, in the same

manner as FCR[1] does for the RHR.

THR Trigger levels:

FCR[3]: Tx trigger level enable

logic 0 âTransmit trigger levels enabled

logic 1 âTransmit trigger levels disabled

When FCR[3]=0, the transmitter trigger level is always set

to 1, thus ignoring FCR[5:4]. Alternatively, 950-mode

trigger levels can be set using ACR[5].

FCR[5:4]: Compatible trigger levels

450, 550 and extended 550 modes:

The transmitter interrupt trigger levels are set to 1 and

FCR[5:4] are ignored.

650 mode:

In 650 mode the transmitter interrupt trigger levels can be

set to the following values:

FCR[5:4]

Transmit Interrupt Trigger level

112

Table 19: Transmit Interrupt Trigger Levels

These levels only apply when in Enhanced mode and when

FCR[3] is set, otherwise the trigger level is set to 1. A

transmitter empty interrupt will be generated (if enabled) if

the TFL falls below the trigger level.

750 Mode:

In 750 compatible mode, transmitter trigger level is set to 1,

FCR[4] is unused and FCR[5] defines the FIFO depth as

follows:

FCR[5]=0: FIFO size is 16 bytes.

FCR[5]=1: FIFO size is 128 bytes.

In non-Enhanced mode and when FIFOSEL pin is low,

FCR[5] is writable only when LCR[7] is set. Note that in

Enhanced mode, the FIFO size is increased to 128 bytes

when FCR[0] is set.

DS-0029 Jul 05

ExternalâFree Release

Page 36

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