OX16PCI954_05 Datasheet, PDF (21/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
Bits
17:16
19:18
21:20
23:22
31:24
Description
MIO8 Configuration Register.
00 -> MIO8 is a non-inverting input pin
01 -> MIO8 is an inverting input pin
10 -> MIO8 is an output pin driving ‘0’
11 -> MIO8 is an output pin driving ‘1’
MIO9 Configuration Register.
00 -> MIO9 is a non-inverting input pin
01 -> MIO9 is an inverting input pin
10 -> MIO9 is an output pin driving ‘0’
11 -> MIO9 is an output pin driving ‘1’
MIO10 Configuration Register.
00 -> MIO10 is a non-inverting input pin
01 -> MIO10 is an inverting input pin
10 -> MIO10 is an output pin driving ‘0’
11 -> MIO10 is an output pin driving ‘1’
MIO11 Configuration Register.
00 -> MIO11 is a non-inverting input pin
01 -> MIO11 is an inverting input pin
10 -> MIO11 is an output pin driving ‘0’
11 -> MIO11 is an output pin driving ‘1’
Reserved
OX16PCI954
Read/Write
EEPROM
PCI
W
RW
Reset
00
W
RW
00
W
RW
00
W
RW
00
-
R
00h
6.4.3 Local Bus Timing Parameter register 1 ‘LT1’ (Offset 0x08):
The Local Bus Timing Parameter registers (LT1 and LT2) define the operation and timing parameters used by the Local Bus.
The timing parameters are programmed in 4-bit registers to define the assertion/de-assertion of the Local Bus control signals.
The value programmed in these registers defines the number of PCI clock cycles after a Reference Cycle when the events
occur, where the reference Cycle is defined as two clock cycles after the master asserts the IRDY# signal. The following
arrangement provides a flexible approach for users to define the desired bus timing of their peripheral devices. The timings refer
to I/O or Memory mapped access to BAR0 and BAR1 of Function1.
Bits
Description
Read/Write
Reset
EEPROM _PCI
3:0
Read Chip-select Assertion (Intel-type interface). Defines the number of
W
RW
0h
clock cycles after the Reference Cycle when the LBCS[3:0]# pins are
asserted (low) during a read operation from the Local Bus.¹
These bits are unused in Motorola-type interface.
7:4
Read Chip-select De-assertion (Intel-type interface). Defines the number
W
RW
3h
of clock cycles after the Reference Cycle when the LBCS[3:0]# pins are
(2h for
de-asserted (high) during a read from the Local Bus. ¹
parallel port)
These bits are unused in Motorola-type interface.
11:8
Write Chip-select Assertion (Intel-type interface). Defines the number of
W
RW
0h
clock cycles after the Reference Cycle when the LBCS[3:0]# pins are
asserted (low) during a write operation to the Local Bus. ¹
These bits are unused in Motorola-type interface.
DS-0029 Jul 05
External—Free Release
Page 21