OX16PCI954_05 Datasheet, PDF (22/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
Bits
15:12
Description
Write Chip-select De-assertion (Intel-type interface). Defines the number
of clock cycles after the reference cycle when the LBCS[3:0]# pins are
de-asserted (high) during a write operation to the Local Bus. ¹
Read/Write
EEPROM _PCI
W
RW
Reset
2h
Read-not-Write De-assertion during write cycles (Motorola-type
interface). Defines the number of clock cycles after the reference cycle
when the LBRDWR# pin is de-asserted (high) during a write to the Local
Bus. ¹
19:16
Read Control Assertion (Intel-type interface). Defines the number of
W
clock cycles after the Reference Cycle when the LBRD# pin is asserted
(low) during a read from the Local Bus. ¹
RW
0h
(1h for
parallel port)
Read Data-strobe Assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are asserted (low) during a read from the Local Bus. ¹
23:20
Read Control De-assertion (Intel-type interface). Defines the number of
W
clock cycles after the Reference Cycle when the LBRD# pin is de-
asserted (high) during a read from the Local Bus. ¹
RW
3h
(2h for
parallel port)
Read Data-strobe De-assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are de-asserted (high) during a read from the Local Bus. ¹
27:24
Write Control Assertion (Intel-type interface). Defines the number of
W
clock cycles after the Reference Cycle when the LBWR# pin is asserted
(low) during a write to the Local Bus. ¹
RW
0h
(1h for
parallel port)
Write Data-strobe Assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are asserted (low) during a write to the Local Bus. ¹
31:28
Write Control De-assertion (Intel-type interface). Defines the number of
W
RW
2h
clock cycles after the Reference Cycle when the LBWR# pin is de-
asserted (high) during a write to the Local Bus. ¹
Write Data-strobe De-assertion (Motorola-type interface). Defines the
number of clock cycles after the Reference Cycle when the LBDS[3:0]#
pins are de-asserted (high) during a write cycle to the Local Bus. ¹
Note 1: Only values in the range of 0h to Ah (0-10 decimal) are valid. Other values are reserved. These parameters apply to both 8-bit and 32-bit Local Bus
configurations. See notes in the following page.
DS-0029 Jul 05
External—Free Release
Page 22