OX16PCI954_05 Datasheet, PDF (4/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
7.5.2 LINE CONTROL REGISTER ‘LCR’............................................................................................................................... 37
7.5.3 LINE STATUS REGISTER ‘LSR’ .................................................................................................................................. 38
7.6 INTERRUPTS & SLEEP MODE........................................................................................................................................ 39
7.6.1 INTERRUPT ENABLE REGISTER ‘IER’....................................................................................................................... 39
7.6.2 INTERRUPT STATUS REGISTER ‘ISR’....................................................................................................................... 40
7.6.3 INTERRUPT DESCRIPTION ........................................................................................................................................ 40
7.6.4 SLEEP MODE ............................................................................................................................................................... 41
7.7 MODEM INTERFACE ....................................................................................................................................................... 41
7.7.1 MODEM CONTROL REGISTER ‘MCR’........................................................................................................................ 41
7.7.2 MODEM STATUS REGISTER ‘MSR’ ........................................................................................................................... 42
7.8 OTHER STANDARD REGISTERS ................................................................................................................................... 42
7.8.1 DIVISOR LATCH REGISTERS ‘DLL & DLM’................................................................................................................ 42
7.8.2 SCRATCH PAD REGISTER ‘SPR’ ............................................................................................................................... 42
7.9 AUTOMATIC FLOW CONTROL....................................................................................................................................... 43
7.9.1 ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................. 43
7.9.2 SPECIAL CHARACTER DETECTION .......................................................................................................................... 44
7.9.3 AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 44
7.9.4 AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 44
7.10 BAUD RATE GENERATION............................................................................................................................................. 45
7.10.1 GENERAL OPERATION ............................................................................................................................................... 45
7.10.2 CLOCK PRESCALER REGISTER ‘CPR’...................................................................................................................... 45
7.10.3 TIMES CLOCK REGISTER ‘TCR’................................................................................................................................. 45
7.10.4 EXTERNAL 1X CLOCK MODE..................................................................................................................................... 47
7.10.5 CRYSTAL OSCILLATOR CIRCUIT .............................................................................................................................. 47
7.11 ADDITIONAL FEATURES ................................................................................................................................................ 47
7.11.1 ADDITIONAL STATUS REGISTER ‘ASR’ .................................................................................................................... 47
7.11.2 FIFO FILL LEVELS ‘TFL & RFL’ ................................................................................................................................... 48
7.11.3 ADDITIONAL CONTROL REGISTER ‘ACR’................................................................................................................. 48
7.11.4 TRANSMITTER TRIGGER LEVEL ‘TTL’ ...................................................................................................................... 49
7.11.5 RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ...................................................................................................... 49
7.11.6 FLOW CONTROL LEVELS ‘FCL’ & ‘FCH’ .................................................................................................................... 49
7.11.7 DEVICE IDENTIFICATION REGISTERS...................................................................................................................... 49
7.11.8 CLOCK SELECT REGISTER ‘CKS’.............................................................................................................................. 50
7.11.9 NINE-BIT MODE REGISTER ‘NMR’ ............................................................................................................................. 50
7.11.10 MODEM DISABLE MASK ‘MDM’ .................................................................................................................................. 51
7.11.11 READABLE FCR ‘RFC’................................................................................................................................................. 51
7.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.................................................................................................................... 51
8 LOCAL BUS ........................................................................................................................................ 52
8.1 OVERVIEW ....................................................................................................................................................................... 52
8.2 OPERATION ..................................................................................................................................................................... 52
8.3 CONFIGURATION & PROGRAMMING............................................................................................................................ 53
9 BIDIRECTIONAL PARALLEL PORT .................................................................................................. 54
9.1 OPERATION AND MODE SELECTION ........................................................................................................................... 54
9.1.1 SPP MODE ................................................................................................................................................................... 54
9.1.2 PS2 MODE.................................................................................................................................................................... 54
9.1.3 EPP MODE ................................................................................................................................................................... 54
9.1.4 ECP MODE (NOT SUPPORTED)................................................................................................................................. 54
9.2 PARALLEL PORT INTERRUPT ....................................................................................................................................... 54
9.3 REGISTER DESCRIPTION............................................................................................................................................... 55
9.3.1 PARALLEL PORT DATA REGISTER ‘PDR’ ................................................................................................................. 55
9.3.2 DEVICE STATUS REGISTER ‘DSR’ ............................................................................................................................ 55
9.3.3 DEVICE CONTROL REGISTER ‘DCR’......................................................................................................................... 56
9.3.4 EPP ADDRESS REGISTER ‘EPPA’ ............................................................................................................................. 56
9.3.5 EPP DATA REGISTERS ‘EPPD1-4’ ............................................................................................................................. 56
9.3.6 EXTENDED CONTROL REGISTER ‘ECR’................................................................................................................... 56
DS-0029 Jul 05
External—Free Release
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