OX16PCI954_05 Datasheet, PDF (58/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
10.2.2 Zone1: Local Configuration Registers
The Zone1 region of EEPROM contains the program value
of the vendor-specific Local Configuration Registers using
one or more configuration WORDs. Registers are selected
using a 7-bit byte-offset field. This offset value is the offset
from Base Address Registers in I/O or memory space (see
section 6.4).
Note: Not all of the registers in the Local Configuration Register set are
writable by EEPROM. If bit2 of the header is set, Zone1
configuration WORDs follow the header declaration. The
format of configuration WORDs for the Local Configuration
Registers in Zone1 are described in Table 32.
Bits Description
15 ‘0’ = There are no more Configuration WORDs
to follow in Zone1. Move to the next available
zone or end EEPROM program if no more zones
are enabled in the Header.
‘1’ = There is another Configuration WORD to
follow for the Local Configuration Registers.
14:8 These seven bits define the byte-offset of the
Local configuration register to be programmed.
For example the byte-offset for LT2[23:16] is
0x0E.
7:0 8-bit value of the register to be programmed
Table 32: Zone 1 data format
Table 33 shows which Local Configuration registers are writable from the EEPROM. Note that an attempt by the EEPROM to
write to any other offset locations can result in unpredictable behaviour.
Offset
0x00
0x00
0x00
0x00
0x00
0x04
0x05
0x06
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0E
0x0E
0x0F
0x0F
0x0F
0x0F
0x0F
0x1E
0x1E
0x1E
0x1F
Bits
Description
1:0
Must be ‘00’.
2
Enable UART clock-out.
4:3
Endian byte-lane select.
6:5
Power-down filter.
7
MIO2_PME enable.
7:0
Multi-purpose IO configuration.
7:0
Multi-purpose IO configuration.
7:0
Multi-purpose IO configuration.
7:0
Local Bus timing parameters
7:0
Local Bus timing parameters
7:0
Local Bus timing parameters
7:0
Local Bus timing parameters
7:0
Local Bus timing parameters
7:0
Local Bus timing parameters
3:0
Must be ‘0000’.
6:4
IO Space Block size.
7
Lower-Address-CS-Decode.
2:0
Lower-Address-CS-Decode.
4:3
Memory space block size in 32-bit Local Bus.
5
Must be ‘0’.
6
Local Bus clock enable.
7
Bus interface type.
3:0
UART Interrupt Mask
4
MIO0/Parallel Port interrupt mask
7:5
Multi-purpose IO interrupt mask.
7:0
Multi-purpose IO interrupt mask.
Reference
LCC[2]
LCC[4:3]
LCC[6:5]
LCC[7]
MIC[7:0]
MIC[15:8]
MIC[23:16]
LT1[7:0]
LT1[15:8]
LT1[23:16]
LT1[31:24]
LT2[7:0]
LT2[15:8]
LT2[22:20]
LT2[23]
LT2[26:24]
LT2[28:27]
LT2[30]
LT2[31]
GIS[19:16]
GIS[20]
GIS[23:21]
GIS[31:24]
Table 33: EEPROM-writable Local Configuration Registers
DS-0029 Jul 05
External—Free Release
Page 58