OX16PCI954_05 Datasheet, PDF (3/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
CONTENTS
FEATURES ................................................................................................................................................... 1
DESCRIPTION .............................................................................................................................................. 1
CONTENTS................................................................................................................................................... 3
1 PERFORMANCE COMPARISON.......................................................................................................... 6
2 BLOCK DIAGRAM ................................................................................................................................ 7
3 PIN INFORMATION ............................................................................................................................... 8
4 PIN DESCRIPTIONS.............................................................................................................................. 9
5 CONFIGURATION & OPERATION ..................................................................................................... 14
6 PCI TARGET CONTROLLER.............................................................................................................. 15
6.1 OPERATION ..................................................................................................................................................................... 15
6.2 CONFIGURATION SPACE ............................................................................................................................................... 15
6.2.1 PCI CONFIGURATION SPACE REGISTER MAP........................................................................................................ 16
6.3 ACCESSING LOGICAL FUNCTIONS .............................................................................................................................. 17
6.3.1 PCI ACCESS TO INTERNAL UARTS........................................................................................................................... 17
6.3.2 PCI ACCESS TO 8-BIT LOCAL BUS............................................................................................................................ 17
6.3.3 PCI ACCESS TO PARALLEL PORT ............................................................................................................................ 18
6.3.4 PCI ACCESS TO 32-BIT LOCAL BUS.......................................................................................................................... 18
6.4 ACCESSING LOCAL CONFIGURATION REGISTERS................................................................................................... 19
6.4.1 LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ........................................................ 19
6.4.2 MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................ 20
6.4.3 LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): .................................................................. 21
6.4.4 LOCAL BUS TIMING PARAMETER REGISTER 2 ‘LT2’ (OFFSET 0X0C): ................................................................. 23
6.4.5 UART RECEIVER FIFO LEVELS ‘URL’ (OFFSET 0X10)............................................................................................. 24
6.4.6 UART TRANSMITTER FIFO LEVELS ‘UTL’ (OFFSET 0X14)...................................................................................... 24
6.4.7 UART INTERRUPT SOURCE REGISTER ‘UIS’ (OFFSET 0X18)............................................................................... 25
6.4.8 GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X1C) ............................................... 26
6.5 PCI INTERRUPTS............................................................................................................................................................. 27
6.6 POWER MANAGEMENT .................................................................................................................................................. 28
6.6.1 POWER MANAGEMENT OF FUNCTION 0 ................................................................................................................. 28
6.6.2 POWER MANAGEMENT OF FUNCTION 1 ................................................................................................................. 29
7 INTERNAL OX16C950 UARTS ........................................................................................................... 30
7.1 OPERATION – MODE SELECTION ................................................................................................................................. 30
7.1.1 450 MODE..................................................................................................................................................................... 30
7.1.2 550 MODE..................................................................................................................................................................... 30
7.1.3 EXTENDED 550 MODE ................................................................................................................................................ 30
7.1.4 750 MODE..................................................................................................................................................................... 30
7.1.5 650 MODE..................................................................................................................................................................... 30
7.1.6 950 MODE..................................................................................................................................................................... 31
7.2 REGISTER DESCRIPTION TABLES ............................................................................................................................... 32
7.3 RESET CONFIGURATION ............................................................................................................................................... 35
7.3.1 HARDWARE RESET .................................................................................................................................................... 35
7.3.2 SOFTWARE RESET ..................................................................................................................................................... 35
7.4 TRANSMITTER AND RECEIVER FIFOS ......................................................................................................................... 36
7.4.1 FIFO CONTROL REGISTER ‘FCR’ .............................................................................................................................. 36
7.5 LINE CONTROL & STATUS............................................................................................................................................. 37
7.5.1 FALSE START BIT DETECTION.................................................................................................................................. 37
DS-0029 Jul 05
External—Free Release
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