OX16PCI954_05 Datasheet, PDF (18/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
offset is 08-0Fh, LBCS2# when offset is 10-17h, and
LBCS3# when offset is 18- 1Fh.
The region can be divided into two chip-select regions by
selecting the uppermost address bit to decode chip selects.
In the above example, the user can select A4 as the
Lower-Address-CS-Decode, thus using A[5:4] internally to
decode chip selects. As in this example LBA5 is always
zero, only chip-select lines LBCS0# and LBCS1# will be
decoded into, asserting LBCS0# when address offset is 00-
0Fh and LBCS1# when offset is 10-1Fh.
The region can be allocated to a single chip-select region
by assigning an address bit beyond the selected range to
Lower-Address-CS-Decode (but not above A8). In the
above example, if the user selects A5 as the Lower-
Address-CS-Decode, A[6:5] will be used to internally
decode chip-selects. As in this example LBA[7:5] are
always zero, only the chip select line LBCS0# may be
selected. In this case address offset 00-1Fh asserts
LBCS0# and the other chip-select lines remain inactive
permanently.
With default values, the address map for local bus IO
address accesses is the same as for internal UARTs.
Memory Space:
The memory base address registers have an allocated
fixed size of 4K bytes in the address space. Since the
Local Bus has 8 address lines and the OX16PCI954 only
implements DWORD aligned accesses in memory space,
the 256 bytes of addressable space per chip select is
expanded to 1K. Unlike an I/O access, for a memory
access the upper address lines are always active and the
internal chip-select decoding logic ignores the user setting
for Lower-Address-CS-Decode (LT2[26:23]) and uses PCI
AD[11:10] to decode into 4 chip-select regions. When the
Local Bus is accessed in memory space, A[9:2] are
asserted on LBA[7:0]. The chip-select regions are defined
below.
Local Bus
Chip-Select
(Data-Strobe)
LBCS0# (LBDS0#)
LBCS1# (LBDS1#)
LBCS2# (LBDS2#)
LBCS3# (LBDS3#)
PCI Offset from BAR 1 in
Function1 (Memory space)
Lower Address Upper Limit
000h
3FCh
400h
7FCh
800h
BFCh
C00h
FFCh
Table 8: PCI address map for local bus (memory)
Note: The description given for I/O and memory accesses
is for an Intel-type configuration for the Local Bus. For
Motorola-type configuration, the chip select pins are
OX16PCI954
redefined to data strobe pins. In this mode the Local Bus
offers up to 8 address lines and four data-strobe pins.
6.3.3 PCI access to parallel port
When the parallel port is enabled (Mode 01), access to the
port works via BAR definitions as usual, except that there
are two I/O BARs corresponding to the two sets of registers
defined to operate an IEEE1284 EPP and bi-directional
Parallel Port.
The user can change the I/O space block size of BAR0 by
over-writing the default values in LT2[25:20] using the
serial EEPROM (see section 6.4). For example the user
can reduce the allocated space for BAR0 to 4-bytes by
setting LT2[22:20] to ‘001’. The I/O block size allocated to
BAR1 is fixed at 8-Bytes.
Legacy parallel ports expect the upper register set to be
mapped 0x400 above the base block, therefore if the BARs
are fixed with this relationship, generic parallel port drivers
can be used to operate the device in all modes.
Example: BAR0 = 0x00000379 (8 bytes at address 0x378)
BAR1 = 0x00000779 (8 bytes at address 0x778)
If this relationship is not used, custom drivers will be
needed.
6.3.4 PCI access to 32-bit local bus
Access to the Local Bus in 32-bit mode is similar to 8-bit
mode (see section 6.3.2) with the following exceptions:
• The local Bus offers a 32-bit bi-directional data bus
and 12 bit address bus
• The PCI address signals ‘AD[13:2]’ are asserted on
LBA[11:0]
• Block size in memory space is programmable by
LT2[28:27] (see section 6.4)
• The Lower-Address-CS-Decode (LT2[26:23])
parameter is used to decode up to 4 chip selects
The block size allocation for chip-select regions is defined
in Table 9.
Number
of Chip
selects
1
2
4
1
2
4
Memory
block size
(Kbytes)
16
16
16
4
4
4
LT2[28:27]
‘01’
‘01’
‘01’
‘00’
‘00’
‘00’
LT2[26:23]
‘1010’
‘1001’
‘1000’
‘1000’
‘0111’
‘0110’
Table 9: PCI access to 32-bit local bus (memory)
DS-0029 Jul 05
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