OX16PCI954_05 Datasheet, PDF (19/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
6.4 Accessing Local configuration registers
The local configuration registers are a set of device specific registers which can be accessed from either function. They are
mapped to the I/O and memory addresses set up in BAR2 and BAR3 of each function, with the offsets defined for each register.
Access is limited to byte only for I/O accesses; memory accesses can also be word or dword accessed, however on little-endian
systems such as Intel 80x86 the byte order will be reversed.
6.4.1 Local Configuration and Control register ‘LCC’ (Offset 0x00)
This register defines control of ancillary functions such as Power Management, external clock reference signals and the serial
EEPROM. The individual bits are described below.
Bits Description
Read/Write
EEPROM _PCI
1:0
Mode. These bits return the state of the Mode[1:0] pins.
-
R
2
Enable UART clock output. When this bit is set, the buffered UART clock
W
RW
output pin (UART_CLK_Out) is active. When low UART_CLK_Out is
permanently low.
4:3
Endian Byte-Lane Select for memory access to 8-bit peripherals.
W
RW
00 = Select Data[7:0]
10 = Select Data[23:16]
01 = Select Data[15:8]
11 = Select Data[31:24]
Memory access to OX16PCI954 is always DWORD aligned. When
accessing 8-bit regions like the internal UARTs, the 8-bit Local Bus and
the parallel port, this option selects the active byte lane. As both PCI and
PC architectures are little endian, the default value will be used by
systems, however, some non-PC architectures may need to select the
byte lane. These bits are ignored in 32-bit Local Bus.
6:5
Power-down filter time. These bits define a value of an internal filter time
W
RW
for power-down interrupt request in power management circuitry in
Function0. Once Function0 is ready to go into power down mode,
OX16PCI954 will wait for the specified filter time and if Function0 is still
in power-down request mode, it can assert a PCI interrupt (see section
6.6).
00 = power-down request disabled
10 = 129 seconds
01 = 4 seconds
11 = 518 seconds
7
Function1 MIO2_PME Enable. A value of ‘1’ enables MIO2 pin to set the
W
RW
PME_Status in PMCSR register, and hence assert the PME# pin if
enabled. A value of ‘0’ disables MIO2 from setting the PME_Status bit
(see section 6.6).
23:8 Reserved. These bits are used for test purposes. The device driver must
-
R
write zeros to these bits.
24
EEPROM Clock. For PCI read or write to the EEPROM , toggle this bit to
-
W
generate an EEPROM clock (EE_CK pin).
25
EEPROM Chip Select. When 1 the EEPROM chip-select pin EE_CS is
-
W
activated (high). When 0 EE_CS is de-active (low).
26
EEPROM Data Out. For writes to the EEPROM, this output bit is the
-
W
input-data of the EEPROM. This bit is output on EE_DO and clocked into
the EEPROM by EE_CK.
27
EEPROM Data In. For reads from the EEPROM, this input bit is the
-
R
output-data of the EEPROM connected to EE_DI pin.
28
EEPROM Valid. A 1 indicates that a valid EEPROM program is present
-
R
29
Reload configuration from EEPROM. Writing a 1 to this bit re-loads the
-
W
configuration from EEPROM. This bit is self-clearing after EEPROM read
30
Reserved
-
-
31
Reserved
-
R
Reset
XX
0
00
00
0
0000h
0
0
0
X
X
0
0
0
DS-0029 Jul 05
External—Free Release
Page 19