OX16PCI954_05 Datasheet, PDF (27/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
6.5 PCI Interrupts
Interrupts in PCI systems are level-sensitive and can be
shared. There are sixteen sources of interrupt in the
OX16PCI954, one in each UART channel and twelve from
Multi-Purpose IO pins (MIO11 to MIO0). The Parallel Port
and MIO0 share the same interrupt status bit (GIS[4]). The
PCI Power Management power-down interrupt for internal
UARTs (Function0) and MIO1 share the status bit GIS[5].
The Local Bus uses the MIO pins to pass interrupts to the
PCI controller.
All interrupts are routed to the PCI interrupt pins, INTA# or
INTB#. The default routing asserts Function0 interrupts on
INTA# and Function1 interrupts on INTB#. These default
routings may be modified by writing to the Interrupt Pin field
in the configuration registers using the serial EEPROM
facility. The Interrupt Pin field is normally considered a
hard-wired read-only value in PCI. It indicates to system
software which PCI interrupt pin (if any) is used by a
function. The interrupt pin may only be modified using the
serial EEPROM facility, and card developers must not
invoke any combination which violates the PCI
specification. Note that OX16PCI954 only has two PCI
interrupt pins, INTA# and INTB#. If in doubt, the default
routings should be used. Table 10 relates the Interrupt Pin
field to the device pin used.
Interrupt Pin
0
1
2
3 to 255
Device Pin used
None
INTA#
INTB#
Reserved
Table 10: ‘Interrupt pin’ definition
During the system initialisation process and PCI device
configuration, system-specific software reads the interrupt
pin field to determine which (if any) interrupt pin is used by
each function. It programmes the system interrupt router to
logically connect this PCI interrupt pin to a system-specific
interrupt vector (IRQ). It then writes this routing information
to the Interrupt Line field in the function’s PCI configuration
space. Device driver software must then hook the interrupt
using the information in the Interrupt Line field.
Interrupt status for all sixteen sources of interrupt is
available using the GIS register in the Local Configuration
Register set, which can be accessed using I/O or Memory
accessed from both logical functions. This facility enables
each function to snoop on interrupts asserted from the
other function regardless of the interrupt routing.
The interrupt from each UART channel is enabled using
the IER register and the MCR register for that UART. If the
interrupt is enabled and active, then the device will drive
the PCI interrupt pin low. Generic device driver software
will use the IER register to enable interrupts. The
OX16PCI954 offers additional interrupt masking ability
using GIS[19:16] (see section 6.4.8). An internal UART
channel may assert a PCI interrupt if the interrupt is
enabled by IER and GIS[19:16].
All interrupts can be enabled / disabled individually using
the GIS register set in the Local configuration registers.
When an MIO pin is enabled, an external device can assert
a PCI interrupt by driving that pin. The sense of the MIO
external interrupt pins (active-high or active-low) is defined
in the MIC register. The parallel port can also assert an
interrupt (Note: this effectively disables the MIO[0]
interrupt).
DS-0029 Jul 05
External—Free Release
Page 27