OX16PCI954_05 Datasheet, PDF (26/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
6.4.8 Global Interrupt Status and Control Register ‘GIS’ (Offset 0x1C)
Bits Description
Read/Write
EEPROM _PCI
3:0 These bits reflect the state of UART3 to UART0 internal interrupt lines,
-
R
respectively.¹
4
MIO0 (Mode[1:0]≠‘01’). This bit reflects the state of the internal MIO[0]. The
-
R
internal MIO[0] reflects the non-inverted or inverted state of MIO0 pin.²
Reset
0x0h
X
Parallel Port Interrupt (Mode[1:0]=‘01’). This bit reflects the state of the Parallel
Port internal interrupt line.
-
5
MIO1 (LCC[6:5]=‘00’). This bit reflects the state of the internal MIO[1]. The
internal MIO[1] reflects the non-inverted or inverted state of MIO1 pin.²
R
0
R
X
Function0 Power-down Interrupt (LCC[6:5] ≠‘00’). In this mode this is a sticky
bit. When set, it indicates a power-down request issued by Function0 and
would normally have asserted a PCI interrupt if bit 21 was set (see section
7.9). Reading this bit clears it.
15:6 These bits reflect the state of the internal MIO[11:2]. The internal MIO[11:2]
-
reflect the non-inverted or inverted state of MIO[11:2] pins respectively.²
19:16 UART Interrupt Mask. When set (=1) these bit enable each internal UART to W
assert a PCI interrupt respectively. When cleared (=0) they prevent the
respective channel from asserting a PCI interrupt.³
20
MIO[0] Interrupt Mask (Mode[1:0]≠‘01’). When set (=1) this bit enables MIO0
W
pin to assert a PCI interrupt. When cleared (=0) it prevents MIO0 pin from
asserting a PCI interrupt.²
0
R
XXXh
RW
Fh
RW
1
Parallel Port Interrupt Mask (Mode[1:0]=‘01’). When set (=1) this bit enables
W
RW
1
the Parallel Port to assert a PCI interrupt. When cleared (=0) it prevents the
Parallel Port from asserting a PCI interrupt.
21
MIO[1] Interrupt Mask (LCC[6:5]=‘00’). When set (=1) this bit enables MIO1 pin
W
RW
1
to assert a PCI interrupt. When cleared (=0) it prevents MIO1 pin from
asserting a PCI interrupt.²
Function0 Power-down Interrupt Mask (LCC[6:5] ≠‘00’). When set (=1) this bit
W
enables the power-down logic in Function0 to assert a PCI interrupt. When
cleared (=0) it prevents the power-down logic in Function0 from asserting a
PCI interrupt.
31:22 MIO Interrupt Mask. When set (=1) these bits enable each MIO[11:2] pin to
W
assert a PCI interrupt respectively. When cleared (=0) they prevent the
respective pins from asserting a PCI interrupt.²
RW
0
RW
3FFh
Note 1:
Note 2:
Note 3:
Note 4:
GIS[3:0] are the inverse of UIS[24], UIS[18], UIS[6] and UIS[0] respectively. Systems that do not require the Local Bus or parallel port need not read
this register to identify the source of the interrupt as long as they read the UIS (offset 18h) register.
The returned value is either the direct state of the corresponding MIO pin or its inverse as configured by the Multi-purpose I/O Configuration register
‘MIC’ (offset 0x04). As the internal MIO can assert a PCI interrupt, the inversion feature can define each external interrupt to be defined as active-low
or active-high, as controlled by the MIC register.
The UART Interrupt Mask register bits are all set after a hardware reset to enable the interrupt from all internal UARTs. This will cater for generic
device-driver software that does not access the Local Configuration Registers. The default setting for UART Interrupt Mask bits can be changed
using the serial EEPROM. Note that even though by default the UART interrupts are enabled in this register, since after a reset the IER registers of
individual UARTs disables all interrupts, a PCI interrupt will not be asserted after a hardware reset.
When Mode[1:0]=‘10’, the MIO pins are used to define a Subsystem ID value, therefore all interrupts due to MIO pins are disabled regardless of the
state of the GIS register. The MIO Interrupts Mask register bits are all set after a hardware reset to enable the interrupt from all MIO pins from boot
up. The default setting for MIO Interrupt Mask bits can be changed using the serial EEPROM.
DS-0029 Jul 05
External—Free Release
Page 26