OX16PCI954_05 Datasheet, PDF (16/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
6.2.1 PCI Configuration Space Register map
Configuration Register Description
31
16
15
0
Device ID
Vendor ID
Status
Command
Class Code
Revision ID
BIST¹
Header Type
Reserved
Reserved
Base Address Register 0 (BAR0)
Base Address Register 1 (BAR 1)
Base Address Register 2 (BAR 2) – Local Configuration Registers in IO space
Base Address Register 3 (BAR3) – Local Configuration Registers in Memory space
Reserved
Reserved
Reserved
Subsystem ID
Subsystem Vendor ID
Reserved
Reserved
Cap_Ptr
Reserved
Reserved
Reserved
Interrupt Pin
Interrupt Line
Power Management Capabilities (PMC)
Next Ptr
Cap_ID
Reserved
Reserved
PMC Control/Status Register (PMCSR)
Table 4: PCI Configuration space
Offset
Address
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
44h
Register name
Vendor ID
Device ID
Command
Status
Revision ID
Class code
Header type
BAR 0
BAR 1
BAR 2
BAR 3
Subsystem VID
Subsystem ID
Cap ptr.
Interrupt line
Interrupt pin
Cap ID
Next ptr.
PM capabilities
PMC control/
status register
Function 0
UARTs Disabled
0x1415
0x9501 0x9500
0x0000
0x0290
0x00
0x070006
0x80
0x00000001
0x00000000
0x00000001
0x00000000
0x1415
0x0000
0x40
0x00
0x01
0x01
0x00
0x6C01
0x0000
Reset value
Function 1
8-bit bus 32-bit parallel
bus
port
0x1415
0x9511 0x9512 0x9513
0x0000
0x0290
0x00
0x068000 0x068000 0x070101
0x80
0x00000001
0x00000000
00000001
0x00000001
0x00000000
0x1415
0x0000
0x40
0x00
0x02
0x01
0x00
0x6C01
0x0000
Disabled
0x9510
0x068000
00000000
Table 5: PCI configuration space default values
Program read/write
EEPROM PCI
W
R
W
R
-
R/W
W (bit 4) R/W
-
R
W
R
-
R
-
R/W
-
R/W
-
R/W
-
R/W
W
R
W
R
-
R
-
R/W
W
R
-
R
-
R
W
R
-
R/W
DS-0029 Jul 05
External—Free Release
Page 16