OX16PCI954_05 Datasheet, PDF(62/73 Page) Oxford Semiconductor – Integrated Quad UART and PCI interface

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OX16PCI954_05 Datasheet, PDF (62/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

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OXFORD SEMICONDUCTOR LTD.

OX16PCI954

13 AC ELECTRICAL CHARACTERISTICS

13.1 PCI Bus

The timings for PCI pins comply with PCI Specification for the 5.0 Volt signalling environment.

13.2 Local Bus

By default, the Local bus control signals change state in the cycle immediately following the reference cycle, with offsets to

provide setup and hold times for common peripherals in Intel mode. The tables below show these default values; however each

of these can be increased or decreased by an number of PCI clock cycles by adjusting the parameters in registers LT1 and LT2.

Symbol

tref

tza

tard

tzrcs1

tzrcs2

tcsrd

trdcs

tzrd1

tzrd2

tdrd

tzd1

tzd2

tsd

thd

Parameter

IRDY# falling to reference LBCLK

Reference LBCLK to Address Valid

Address Valid to LBRD# falling

Reference LBCLK to LBCS# falling

Reference LBCLK to LBCS# rising

LBCS# falling to LBRD# falling

LBRD# rising to LBCS# rising

Reference LBCLK to LBRD# falling

Reference LBCLK to LBRD# rising

Data bus floating to LBRD# falling

Reference LBCLK to data bus floating at the start of the read

transaction

Reference LBCLK to data bus driven by OX16PCI954 at the end of the

read transaction

Data bus valid to LBRD# rising

Data bus valid after LBRD# rising

Min

Max

Units

Nominally 2 PCI clock cycles

TBD

Table 42: Read operation from Intel-type Local Bus

Symbol

tref

tza

tawr

tzwcs1

tzwcs2

tcswr

twrcs

tzwr1

tzwr2

tzdv

tzdf

twrdi

Parameter

IRDY# falling to reference LBCLK

Reference LBCLK to Address Valid

Address Valid to LBWR# falling

Reference LBCLK to LBCS# falling

Reference LBCLK to LBCS# rising

LBCS# falling to LBWR# falling

LBWR# rising to LBCS# rising

Reference LBCLK to LBWR# falling

Reference LBCLK to LBWR# rising

Reference LBCLK to data bus valid

Reference LBCLK to data bus high-impedance

LBWR# rising to data bus invalid

Min

Max

Units

Nominally 2 PCI clock cycles

TBD

Table 43: Write operation to Intel-type Local Bus

DS-0029 Jul 05

ExternalâFree Release

Page 62

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