OX16PCI954_05 Datasheet, PDF (35/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
7.3 Reset Configuration
7.3.1 Hardware Reset
After a hardware reset, all writable registers are reset to
0x00, with the following exceptions:
DLL, which is reset to 0x01.
CPR, which is reset to 0x20.
The state of read-only registers following a hardware reset
is as follows:
RHR[7:0]: Indeterminate
RFL[6:0]: 00000002
TFL[6:0]: 00000002
LSR[7:0]: 0x60 signifying that both the transmitter and the
transmitter FIFO are empty
MSR[3:0]: 00002
MSR[7:4]: Dependent on modem input lines DCD, RI,
DSR and CTS respectively
ISR[7:0]: 0x01, i.e. no interrupts are pending
ASR[7:0]: 1xx000002
The reset state of output signals are tabulated below:
Signal
SOUT
RTS#
DTR#
Reset state
Inactive High
Inactive High
Inactive High
Table 18: Output Signal Reset State
7.3.2 Software Reset
An additional feature available in the OX16C950 UART is
software resetting of the serial channel. This command has
the same effect on a single channel as a hardware reset
except it does not reset the clock source selections (i.e.
CKS register). To reset the UART write 0x00 to the
Channel Software Reset register ‘CSR’.
DS-0029 Jul 05
External—Free Release
Page 35