OX16PCI954_05 Datasheet, PDF (57/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
10 SERIAL EEPROM
10.1 Specification
The OX16PCI954 can be configured using an optional
serial electrically-erasable programmable read only
memory (EEPROM). If the EEPROM is not present, the
device will remain in its default configuration after reset.
Although this may be adequate for some applications,
many will benefit from the degree of programmability
afforded by this feature.
The EEPROM interface is based on the 93C46/56 serial
EEPROM devices which have a proprietary serial interface
known as Microwire^TM. The interface has four pins which
supply the memory device with a clock, a chip-select, and
serial data input and output lines. In order to read from
such a device, a controller has to output serially a read
command and address, then input serially the data. The
93C46/56 and compatible devices have a 16-bit data word
format but differ in memory size (and number of address
bits).
The OX16PCI954 incorporates a controller module which
reads data from the serial EEPROM and writes data into
the configuration register space. It performs this operation
in a sequence which starts immediately after a PCI bus
reset and ends either when the controller finds no
EEPROM is present or when it reaches the end of its data.
The operation of this controller is described below.
Following device configuration, driver software can access
the serial EEPROM through four bits in the device-specific
Local Configuration Register LCC[27:24]. Software can use
this register to manipulate the device pins in order to read
and modify the EEPROM contents.
The OX16PCI954 requires a total of 82 bytes of EEPROM
data to program all the EEPROM writable registers. Note
that 93C46 and 93C56 EEPROM devices offer 128 and
256 bytes of programmable data respectively.
A Windows® based utility to program the EEPROM is
available. For further details please contact Oxford
Semiconductor (see back cover).
Microwire^TM is a trade mark of National Semiconductor. For
a description of MicroWire, please refer to National
Semiconductor data manuals.
10.2 EEPROM Data Organisation
The serial EEPROM data is divided in four zones. The size
of each zone is an exact multiple of 16-bit WORDs. Zone0
is allocated to the header. A valid EEPROM program must
contain a header. The EEPROM can be programmed from
the PCI bus. Once the programming is complete, the
device driver should either reset the PCI bus or set
LCC[29] to reload the OX16PCI954 registers from the
serial EEPROM. The general EEPROM data structure is
shown in Table 31.
DATA
Zone
0
1
2
3
Size (Words)
One
One or more
One to four
Two or more
Description
Header
Local Configuration Registers
Identification Registers
PCI Configuration Registers
Table 31: EEPROM data format
10.2.1 Zone0: Header
The header identifies the EEPROM program as valid.
Bits Description
15:4 These bits should return 0x950 to identify a valid
program. Once the OX16PCI954 reads 0x950
from these bits, it sets LCC[28] to indicate that a
valid EEPROM program is present.
3 Reserved. Write ‘0’ to this bit.
2 1 = Zone1 (Local Configuration) exists
0 = Zone1 does not exist
1 1 = Zone2 (Identification) exists
0 = Zone2 does not exist
0 1 = Zone3 (PCI Configuration) exists
0 = Zone3 does not exist
The programming data for each zone follows the
proceeding zone if it exists. For example a Header value of
0x9507 indicates that all zones exist and they follow one
another in sequence, while 0x9505 indicates that only
Zones 1 and 3 exist where the header data is followed by
Zone1 WORDs, and since Zone2 is missing Zone1
WORDs are followed by Zone3 WORDs.
DS-0029 Jul 05
External—Free Release
Page 57