OX16PCI954_05 Datasheet, PDF (23/73 Pages) Oxford Semiconductor – Integrated Quad UART and PCI interface

OXFORD SEMICONDUCTOR LTD.
OX16PCI954
6.4.4 Local Bus Timing Parameter register 2 ‘LT2’ (Offset 0x0C):
Bits
3:0
7:4
11:8
15:12
19:16
22:20
26:23
28:27
Description
Write Data Bus Assertion. This register defines the number of clock
cycles after the Reference Cycle when the LBD pins actively drive the
data bus during a write operation to the Local Bus. ¹
Write Data Bus De-assertion. This register defines the number of clock
cycles after the Reference Cycle when the LBD pins go high-impedance
during a write operation to the Local Bus. ^1,2
Read Data Bus Assertion. This register defines the number of clock
cycles after the Reference Cycle when the LBD pins actively drive the
data bus at the end of a read operation from the Local Bus. ¹
Read Data Bus De-assertion. This register defines the number of clock
cycles after the Reference Cycle when the LBD pins go high-impedance
during at the beginning of a read cycle from the Local Bus. ¹
Reserved.
IO Space Block Size of BAR0 in Function1.
000 = Reserved
100 = 32 Bytes
001 = 4 Bytes
101 = 64 Bytes
010 = 8 Bytes
110 = 128 Bytes
011 = 16 Bytes
111 = 256 Bytes
Local Bus Chip–select Parameter ‘Lower-Address-CS-Decode’. ²
IO space in 8-bit Local Bus
Memory space and IO space in
32-bit Local Bus
0000 = A2
1000 = Res
0000 = A4
1000 = A12
0001 = A3
1001 = Res
0001 = A5
1001 = A13
0010 = A4
1010 = Res
0010 = A6
1010 = A14
0011 = A5
1011 = Res
0011 = A7
1011 = Res
0100 = A6
1100 = Res
0100 = A8
1100 = Res
0101 = A7
1101 = Res
0101 = A9
1101 = Res
0110 = A8
1110 = Res
0110 = A10
1110 = Res
0111 = A9
1111 = Res
0111 = A11
1111 = Res
Memory Space Block Size of BAR1 in Function1 (Mode[1:0]=‘11’, i.e. 32-
bit Local Bus).
Read/Write
EEPROM _PCI
W
RW
Reset
0h
W
RW
Fh
W
RW
4h
(2h for
parallel port)
W
RW
0h
-
R
0h
W
R
‘100’
(=‘010’
for parallel
port)
W
RW ‘0001’
(=‘0010’
for parallel
port)
W
R
00
00 = 4 Kbytes
01 = 16 Kbytes
10 = Reserved
11 = Reserved
When 8-bit Local Bus or Parallel Port is selected (Mode[1:0]=‘00’ or ‘01’),
the Memory Block size is fixed at 4K and these bits are ignored.
29
Local Bus Software Reset. When this bit is a 1 the Local Bus reset pin is
-
RW
0
activated. When this bit is a 0 the Local Bus reset pin is de-activated. ³
30
Local Bus Clock Enable. When this bit is a 1 the Local Bus clock (LBCK)
W
RW
0
pin is enabled. When this bit is a 0 LBCK pin is permanently low. The
Local Bus Clock is a buffered PCI clock.
31
Bus Interface Type. When low (=0) the Local Bus is configured to Intel-
W
RW
0
type operation, otherwise it is configured to Motorola-type operation.
Note that when Mode[1:0] is ‘01’, this bit is hard wired to 0.
Note 1: Only values in the range of 0 to Ah (0-10 decimal) are valid. Other values are reserved as writing higher values causes the PCI interface to retry all
accesses to the Local Bus as it is unable to complete the transaction in 16 PCI clock cycles.
Note 2: The Lower-Address-CS-Decode parameter is described in sections 6.3.2 & 6.3.4. These bits are unused for Memory access to the 8-bit Local Bus
which uses a fixed decoding to allocate 1K regions to 4 chip selects. For further information on the Local bus, see section 8.
Note 3: Local Bus, UARTs and the Parallel Port are all reset with PCI reset. In Addition, the user can issue the Software Reset Command.
DS-0029 Jul 05
External—Free Release
Page 23