OXCFU950_07 Datasheet, PDF (61/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
8.11.11 Good-data status register—GDS
The GDS register is available directly in OXCFU950
specific register space at 0x0F. It is also accessible at
offset 0x10 of the ICR.
Good data status is set when the following conditions are
true:
• ISR reads level0 (no interrupt), level2 or 2a
(receiver data) or level3 (THR empty) interrupt.
• LSR[7] is clear i.e. no parity error, framing error
or break in the FIFO.
• LSR[1] is clear i.e. no overrun error has occurred.
GDS[0]: Good Data Status
GDS[7:1]: Reserved
8.11.12 DMA Status Register—DMS
The DMS register is located at offset 0x11 of the ICR. This
register is unused in the OXCFU950 except for test
purposes.
8.11.13 Port Index Register—PIX
The PIX register is located at offset 0x12 of the ICR. This
read-only register gives the UART index. For a single
channel device such as the OXCFU950 this reads 0.
OXCFU950 DATA SHEET
8.11.14 Alternative UART Baud Rate Control
Registers: A_LATCH, A_ENABLE, A_DLL,
A_DLM, A_CPR, A_TCR
Table 18 shows the set of OXCFU950-specific alternative
UART baud rate control registers, which can be used
instead of the standard versions of these registers. This
facility prevents legacy drivers with knowledge of the 950
UART register set from making incorrect assumptions
about the OXCFU950 crystal frequency and synthesize
incorrect baud rate values by writing to the standard DLL,
DLM, CPR and TCR registers. See 8.10.4 for further
details.
8.11.15 Alternative 32-Bit FIFO Access Enable:
DBURST
Table 18 shows the DBURST, the Alternative 32-bit FIFO
Access Registers Enable. The 32-bit FIFO Access
registers can be accessed at 0x00 through 0x03, when
DBURST is set to 0x01. This is for systems where the
UART must be mapped to an8-byte address space. See
8.4.1 for further details.
DS-0023 February 2007
External—Free Release
Page 61 of 74