OXCFU950_07 Datasheet, PDF (47/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
FiCR
Mode
[7:6]
650
750
550
FIFO Size 128 FIFO Size 128 FIFO Size 16
L1
L2 L1
L2
L1 L2
00
1
16 1
1
n/a 1
01
16
32 1
32 n/a 4
10
32 112 1
64 n/a 8
11
112 120 1
112 n/a 14
Table 21: Receiver Trigger Levels
8.5 Line Control & Status
8.5.1 False Start Bit Detection
On the falling edge of a start bit, the receiver waits for 1/2
bit and then resynchronizes the receiver’s sampling clock
to the centre of the start bit. The start bit is valid if the SIN
line is still low at this mid-bit sample and the receiver
proceeds to read in a data character. Verifying the start bit
prevents the receiver from assembling a false data
character due to a low going noise spike on the SIN input.
When the first stop bit is sampled, the received data is
transferred to the RHR and the receiver waits for a low
transition on SIN signifying the next start bit.
The receiver continues to receive data even if the RHR is
full or has been disabled (see section 8.11.3) in order to
maintain framing synchronization. The only difference is
that the received data is not transferred to the RHR.
8.5.2 Line Control Register—LCR
The LCR specifies the data format that is common to both
transmitter and receiver. Writing 0xBF to LCR enables
access to the EFR, XON1, XOFF1, XON2 and XOFF2,
DLL and DLM registers. This value (0xBF) corresponds to
an unused data format. Writing the value 0xBF to LCR will
set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not
affected. Write the desired LCR value to exit from this
selection.
LCR[1:0]: Data length
LCR[1:0] Determines the data length of serial characters.
Note however, that these values are ignored in 9-bit data
framing mode, i.e. when NMR[0] is set.
LCR[1:0]
00
01
10
11
Data length
5 bits
6 bits
7 bits
8 bits
Table 22: LCR Data Length Configuration
OXCFU950 DATA SHEET
In byte mode (450 mode) the trigger levels are all set to 1.
In all cases, a receiver data interrupt is generated (if
enabled) if the Receiver FIFO Level (RFL) reaches the
upper trigger level L2.
950 Mode:
When 950 trigger levels are enabled (ACR[5]=1), more
flexible trigger levels can be set by writing to the TTL, RTL,
FCL and FCH (see section 8.11) hence ignoring FiCR[7:6].
LCR[2]: Number of stop bits
LCR[2] defines the number of stop bits per serial character.
LCR[2]
0
1
1
Data length
5,6,7,8
5
6,7,8
No. stop bits
1
1.5
2
Table 23: LCR Stop Bit Number Configuration
LCR[5:3]: Parity type
The selected parity type will be generated during
transmission and checked by the receiver, which may
produce a parity error as a result. In 9-bit mode parity is
disabled and LCR[5:3] is ignored.
LCR[5:3]
xx0
001
011
101
111
Parity type
No parity bit
Odd parity bit
Even parity bit
Parity bit forced to 1
Parity bit forced to 0
Table 24: LCR Parity Configuration
LCR[6]: Transmission break
logic 0 ⇒ Break transmission disabled.
logic 1 ⇒ Forces the transmitter data output SOUT low
to alert the communication terminal, or send
zeros in IrDA mode.
The software driver must ensure that the break duration is
longer than the character period for it to be recognized
remotely as a break rather than data.
LCR[7]: Divisor latch enable
logic 0 ⇒ Access to DLL & DLM registers disabled.
logic 1 ⇒ Access to DLL & DLM registers enabled.
DS-0023 February 2007
External—Free Release
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