OXCFU950_07 Datasheet, PDF (49/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
8.6 UART Interrupts
The serial interrupt on the OXCFU950 is routed to the
OXCFU950 interrupt control, regardless of MCR[3].
8.6.1 Interrupt Enable Register—IER
Serial channel interrupts are enabled using the Interrupt
Enable Register (IER).
IER[0]: Receiver data available interrupt mask
logic 0 ⇒Disable the receiver ready interrupt.
logic 1 ⇒Enable the receiver ready interrupt.
IER[1]: Transmitter empty interrupt mask
logic 0 ⇒Disable the transmitter empty interrupt.
logic 1 ⇒Enable the transmitter empty interrupt.
IER[2]: Receiver status interrupt
Normal mode:
logic 0 ⇒ Disable the receiver status interrupt.
logic 1 ⇒ Enable the receiver status interrupt.
9-bit data mode:
logic 0 ⇒ Disable receiver status & address bit interrupt.
logic 1 ⇒ Enable receiver status & address bit interrupt.
In 9-bit mode (i.e. when NMR[0] is set) reception of a
character with the address-bit (9^th bit) set can generate a
level 1 interrupt if IER[2] is set.
IER[3]: Modem status interrupt mask
logic 0 ⇒ Disable the modem status interrupt.
logic 1 ⇒ Enable the modem status interrupt.
IER[4]: Reserved⁰
IER[5]: Special character interrupt mask¹
9-bit data framing mode:
logic 0 ⇒ Disable the special character receive interrupt.
logic 1 ⇒ Enable the special character receive interrupt.
In 9-bit data mode, The receiver can detect up to four
special characters programmed in Special Character 1 to
4. When IER[5] is set, a level 5 interrupt is asserted when a
match is detected.
650/950 modes (non-9-bit data framing):
logic 0 ⇒ Disable the special character receive interrupt.
logic 1 ⇒ Enable the special character receive interrupt.
OXCFU950 DATA SHEET
In 16C654-compatible mode, when the device is in
enhanced mode (EFR[4]=1), this bit enables the detection
of special characters. It enables both the detection of
XOFF characters (when in-band flow control is enabled via
EFR[3:0]) and the detection of the XOFF2 special
character (when enabled via EFR[5]).
750 mode (non-9-bit data framing):
logic 0 ⇒ Disable alternative sleep mode.
logic 1 ⇒ Enable alternative sleep mode whereby the
internal clock of the channel is switched off.
IER[6]: RTS interrupt mask
logic 0 ⇒ Disable the RTS interrupt.
logic 1 ⇒ Enable the RTS interrupt.
This enable is only operative in enhanced mode
(EFR[4]=1). In non-hnhanced mode, RTS interrupt is
permanently enabled.
IER[7]: CTS interrupt mask
logic 0 ⇒ Disable the CTS interrupt.
logic 1 ⇒ Enable the CTS interrupt.
This enable is only operative in Enhanced mode
(EFR[4]=1). In non-Enhanced mode, CTS interrupt is
permanently enabled.
Note 0:
In the OX16C95x UARTs this bit is used for sleep mode. In the
OXCFU950, sleep management is managed outside of the UART. See
8.6.4. The OXCFU950 UART core has all standard 950 power
management features removed, so that a single clock domain solution is
possible, so sleep mode with this device is not possible. Most OS support
for power management in UART devices is based on waking the device
up on a modem event such as a falling edge on ring indicator (RI). The
UART core contains a single flip-flop that is not on the standard clock
domain, allowing events like these to be signaled to the surrounding logic,
even when the clock is not running.
Note 1:
In the OX16C95x UARTs 16C750-compatible mode this bit is used as an
alternative sleep mode, whcih is not the case with the OXCFU950
DS-0023 February 2007
External—Free Release
Page 49 of 74