OXCFU950_07 Datasheet, PDF (38/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
7.4 Reading from USB Memory
The host must use the following procedure to read from
USB memory:
• Write the memory address into Memory Address 0
and Memory Address 1.
On writing to Memory Address 1, bit 0 of Memory
Control is cleared and set to 1 when the read data is
available for reading from Memory Read Data 0-3.
• Poll Memory Control (0x33) & wait until bit 0 is set.
• Read bits 7:0 of the 32 bit data value from Memory
Read Data 0 (0x38).
• Read bits 15:8 of the 32 bit data value from Memory
Read Data 1 (0x39).
• Read bits 23:16 of the 32 bit data value from Memory
Read Data 2 (0x3A).
• Read bits 31:24 of the 32 bit data value from Memory
Read Data 3 (0x3B).
The data read from USB memory is returned in Memory
Read Data 0-3. The read is initiated every time Memory
Address 1 is written.
7.5 Accessing USB Memory via Common
Memory Access
Due to the limited number of address bits available in the
compact flash form factor (11 address bits) a paging
mechanism must be used if direct access to the USB
Memory (via common memory space) is required. It should
be used as follows.
To access a portion of the USB memory via the common
memory space the host system should follow this
procedure:
• Select the portion of USB memory via the Memory
Page Select (0x40) register.
• Access the page of memory via common memory
space (location 0x0000–0x07FF).
OXCFU950 DATA SHEET
7.6 USB Host Controller Overview
The OXCFU950 USB module uses an OHCI-compliant
USB host controller. This is augmented by a 2-Kbyte x 32-
bit RAM to which both the OHCI controller and the host
machine have access. The host access can be direct via
common memory space or indirect via I/O space.
A USB RAM controller arbitrates between all three sources
of RAM read and writes. The priority of the accesses is
shown below (most important first):
1) CF host read—has to be highest priority because there
are strict requirements of the CF bus to be met. A CF
host read access interrupts and pauses any other
accesses. All other accesses can be held off, and so
do not interrupt a lower priority access.
2) OHCI read/write—the USB host controller should
generally be given priority.
3) CF write access—because this can be queued until the
OHCI read/write has been completed.
4) Indirect I/O access—lowest priority because this can
easily be held off, and doing so should not adversely
affect performance.
The RAM controller is responsible for this arbitration.
The HCI bus controller is responsible for communicating
with the UHOSTC. Local bus indirect access can be
generated either to the UHOSTC register set or to the
RAM. The HCI bus controller must direct these accesses
appropriately.
Note: The USB controller supports all OHCI endpoint
types. However, support is not provided for USB hub
devices.
DS-0023 February 2007
External—Free Release
Page 38 of 74