OXCFU950_07 Datasheet, PDF (44/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
OXCFU950 DATA SHEET
Note 12: The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the indexed control registers
via ICR. Offset values not listed in the table are reserved for future use and must not be used.
To read or write to any of the Indexed Control Registers use the following procedure.
Writing to ICR registers:
Ensure that the last value written to LCR was not 0xBF (reserved for 650 compatible register access value).
Write the desired offset to SPR (address 1112).
Write the desired value to ICR (address 1012).
Reading from ICR registers:
Ensure that the last value written to LCR was not 0xBF (see above).
Write 0x00 offset to SPR to select ACR.
Set bit 6 of ACR (ICR read enable) by writing x1xxxxxx2 to address 1012. Ensure that other bits in ACR are not changed.
(Software drivers should keep a copy of the contents of the ACR elsewhere since reading ICR involves overwriting ACR!)
Write the desired offset to SPR (address 1112).
Read the desired value from ICR (address 1012).
Write 0x00 offset to SPR to select ACR.
Clear bit 6 of ACR bye writing x0xxxxxx2 to ICR, thus enabling access to standard registers again.
Note 13: GDS available directly in OXCFU950 specific register space at 0x0F
Register
SPR R/W Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Name
Offset ¹¹
Indexed Control Register Set – alternative baud rate control registers
A_LATCH 0x30
R/W
To access addresses 0x31 to 0x35 in this alternative register set
the value 0xEB must be written to this location.
A_ENABLE 0x31
R/W
Enables Enables Enables
A_TCR A_CPR A_DLM
A_DLL
0x32
R/W Alternative DLL register.
Bit 0
Enables
A_DLL
A_DLM
A_CPR
0x33
R/W Alternative DLM register.
0x34
R/W Alternative CPR register.
A_TCR
0x35
R/W Alternative TCR register.
0x36
Unused
0x37
Unused
Indexed Control Register Set – Alternative 32-bit FIFO access registers enable
DBURST
0x38
Unused
Table 18: OXCFU950 Specific Alternative UART Baud Rate Control Registers
DBURST
Enable
Table 18 shows the set of OXCFU950 specific alternative UART baud rate control registers, which can be used instead of the
standard versions of these registers. This facility prevents legacy drivers with knowledge of the 950 UART register set from
making incorrect assumptions about the OXCFU950 crystal frequency and synthesizing incorrect baud rate values by writing to
the standard DLL, DLM, CPR and TCR registers. It also shows the Alternative 32-bit FIFO Access Registers Enable.
DS-0023 February 2007
External—Free Release
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