OXCFU950_07 Datasheet, PDF (59/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
8.11.5 Receiver Interrupt. Trigger Level—RTL
The RTL register is located at offset 0x05 of the ICR
Whenever 950 trigger levels are enabled (ACR[5]=1), bits 6
and 7 of FiCR are ignored and an alternative arbitrary
receiver interrupt trigger level can be defined in the RTL
register. This 7-bit value provides a fully programmable
receiver interrupt trigger facility as opposed to the limited
trigger levels available in 16C654 and 16C750 devices. It
enables the system designer to optimize the interrupt
performance hence minimizing the interrupt overhead.
In 950 mode, a priority level 2 interrupt occurs indicating
that the receiver data is available when the interrupt is not
masked (IER[0]=1) and the receiver FIFO level reaches the
value stored in this register.
8.11.6 Flow Control Levels—FCL & FCH
The FCL and FCH registers are located at offsets 0x06 and
0x07 of the ICR respectively
Enhanced software flow control using Xon/Xoff and
hardware flow control using RTS#/CTS# and DTR#/DSR#
are available when 950 mode trigger levels are enabled
(ACR[5]=1). Improved flow control threshold levels are
offered using Flow Control Lower trigger level (FCL) and
Flow Control Higher trigger level (FCH) registers to provide
a greater degree of flexibility when optimizing the flow
control performance. Generally, these facilities are only
available in enhanced mode.
In 650 mode, in-band flow control is enabled using the EFR
register. An Xoff character is transmitted when the receiver
FIFO exceeds the upper trigger level defined by FiCR[7:6]
as described in section 8.4.2. An Xon is then sent when the
FIFO is read down to the lower fill level. The flow control is
enabled and the appropriate mode selected using
EFR[3:0].
In 950 mode, the flow control thresholds defined by
FiCR[7:6] are ignored. In this mode threshold levels are
programmed using FCL and FCH. When in-band flow
control is enabled (defined by EFR[3:0]) and the RFL)
reaches the value programmed in the FCH register, an Xoff
is transmitted to stop the flow of serial data. The flow is
resumed when the receiver FIFO fill level falls to below the
value programmed in the FCL register, at which point an
Xon character is sent. The FCL value of 0x00 is illegal.
For example if FCL and FCH contain 64 and 100
respectively, Xoff is transmitted when the receiver FIFO
contains 100 characters, and Xon is transmitted when
sufficient characters are read from the receiver FIFO such
that 63 characters remain.
OXCFU950 DATA SHEET
CTS/RTS and DSR/DTR out-of-band flow control use the
same trigger levels as in-band flow control. When out-of-
band flow control is enabled, RTS# (or DTR#) line is de-
asserted when the receiver FIFO level reaches the upper
limit defined in the FCH and is re-asserted when the
receiver FIFO is drained below the lower limit defined in
FCL. When 950 trigger levels are enabled (ACR[5]=1), the
CTS# flow control functions as in 650 mode and is
configured by EFR[7]. However, when EFR[6] is set, RTS#
is automatically de-asserted when RFL reaches FCH and
re-asserted when RFL drops below FCL.
DSR# flow control is configured with ACR[2]. DTR# flow
control is configured with ACR[4:3].
8.11.7 Device Identification Registers
The identification registers is located at offsets 0x08 to 0x0B
of the ICR
The 950 offers four bytes of device identification. The
device identification registers may be read using offset
values 0x08 to 0x0B of the Indexed Control Register.
Registers ID1, ID2 and ID3 identify the device as an
OX16C950 type and return 0x16, 0xC9 and 0x50
respectively. The REV register resides at offset 0x0B of
ICR and identifies the revision of CFU950 UART core. This
register returns 0x11 for the OXCFU950.
8.11.8 Nine-bit Mode Register—NMR
The NMR register is located at offset 0x0D of the ICR
The 950 offers 9-bit data framing for industrial multi-drop
applications. 9-bit mode is enabled by setting bit 0 of the
nine-bit mode register (NMR). In 9-bit mode the data length
setting in LCR[1:0] is ignored. Furthermore as parity is
permanently disabled, the setting of LCR[5:3] is also
ignored.
The receiver stores the 9th bit of the received data in
LSR[2] (where parity error is stored in normal mode). Note
that the 950 provides a 128-deep FIFO for LSR[3:1]. The
transmitter FIFO is 9-bit wide and 128 deep. The user
should write the 9th (MSB) data bit in SPR[0] first and then
write the other 8 bits to THR.
As parity mode is disabled, LSR[7] is set whenever there is
an overrun, framing error or received break condition. It is
unaffected by the contents of LSR[2] (Now the received 9th
data bit).
In 9-bit mode, in-band flow control is disabled regardless of
the setting of EFR[3:0] and the Xon1/Xon2/Xoff1 and Xoff2
registers are used for special character detection.
DS-0023 February 2007
External—Free Release
Page 59 of 74