OXCFU950_07 Datasheet, PDF (57/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
OXCFU950 DATA SHEET
8.11 Additional Features
8.11.1 Additional Status Register—ASR
ASR[0]: Transmitter disabled
logic 0 ⇒ The transmitter is not disabled by in-band flow
control.
logic 1 ⇒ The receiver has detected an Xoff, and has
disabled the transmitter.
This bit is cleared after a hardware reset or channel
software reset. The software driver may write 0 to this bit to
re-enable the transmitter if it was disabled by in-band flow
control. Writing 1 to this bit has no effect.
ASR[1]: Remote transmitter disabled
logic 0 ⇒ The remote transmitter is not disabled by in-
band flow control.
logic 1 ⇒ The transmitter has sent an Xoff character, to
disable the remote transmitter. (Cleared when
a subsequent Xon is sent).
This bit is cleared after a hardware reset or channel
software reset. The software driver may write 0 to this bit to
re-enable the remote transmitter (an XON is transmitted).
Writing 1 to this bit has no effect.
Note: The remaining bits (ASR[7:2]) of this register are read only
ASR[2]: RTS
This is the complement of the actual state of the RTS# pin
when the device is not in loopback mode. The driver
software can determine whether the remote transmitter is
disabled by RTS# out-of-band flow control by reading this
bit. In loopback mode this bit reflects the flow control status
rather than the pin’s actual state.
ASR[3]: DTR
This is the complement of the actual state of the DTR# pin
when the device is not in loopback mode. The driver
software can determine whether the remote transmitter is
disabled by DTR# out-of-band flow control by reading this
bit. In loopback mode this bit reflects the flow control status
rather than the pin’s actual state.
ASR[4]: Special character detected
logic 0 ⇒ No special character has been detected.
logic 1 ⇒ A special character has been received and is
stored in the RHR.
This can be used to determine whether a level 5 interrupt
was caused by receiving a special character rather than an
Xoff. The flag is cleared following the read of the ASR.
ASR[5]: RESERVED
This bit is unused in the OXCFU950 and reads 0.
ASR[6]: FIFO size
logic 0 ⇒ FIFOs are 16 deep if FiCR[0] = 1.
logic 1 ⇒ FIFOs are 128 deep if FiCR[0] = 1.
Note: If FiCR[0] = 0, the FIFOs are 1 deep.
ASR[7]: Transmitter Idle
logic 0 ⇒ Transmitter is transmitting.
logic 1 ⇒ Transmitter is idle.
This bit reflects the state of the internal transmitter. It is set
when both the transmitter FIFO and shift register are
empty.
8.11.2 FIFO Fill levels—TFL & RFL
The TFL and RFL registers can be accessed in both the
950-specific registers and the OXCFU950-specific
registers; the latter is the most direct means of access.
The number of characters stored in the THR and RHR can
be determined by reading the TFL and RFL registers
respectively. As the UART clock is asynchronous with
respect to the processor, it is possible for the levels to
change during a read of these FIFO levels. It is therefore
recommended that the levels are read twice and compared
to check that the values obtained are valid. The values
should be interpreted as follows:
1. The number of characters in the THR is no greater
than the value read back from TFL.
2. The number of characters in the RHR is no less than
the value read back from RFL.
8.11.3 Additional Control Register—ACR
The ACR register is located at offset 0x00 of the ICR
ACR[0]: Receiver disable
logic 0 ⇒ The receiver is enabled, receiving data and
storing it in the RHR.
logic 1 ⇒ The receiver is disabled. The receiver
continues to operate as normal to maintain the
framing synchronization with the receive data
stream, but received data is not stored into the
RHR. In-band flow control characters continue
to be detected and acted upon. Special
characters are not detected.
Changes to this bit are only recognized following the
completion of any data reception pending.
DS-0023 February 2007
External—Free Release
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