OXCFU950_07 Datasheet, PDF (53/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
OXCFU950 DATA SHEET
8.9 Automatic Flow Control
Automatic in-band flow control, automatic out-of-band flow
control and special character detection features can be
used in enhanced mode and are software-compatible with
the 16C654. Alternatively, 16C750-compatible automatic
out-of-band flow control can be enabled in non-enhanced
mode. In 950 mode, in-band and out-of-band flow controls
are compatible with 16C654, with the addition of fully
programmable flow control thresholds.
8.9.1 Enhanced Features Register—EFR
Writing 0xBF to LCR enables access to the EFR and other
Enhanced mode registers. This value corresponds to an
unused data format. Writing 0xBF to LCR will set LCR[7]
but leaves LCR[6:0] unchanged. Therefore, the data format
of the transmitter and receiver data is not affected. Write
the desired LCR value to exit from this selection.
Note: in-band transmit and receive flow control is disabled
in 9-bit mode.
EFR[1:0]: In-band receive flow control mode
When in-band receive flow control is enabled, the UART
compares the received data with the programmed Xoff
character(s). When this occurs, the UART disables
transmission as soon as any current character
transmission is complete. The UART then compares the
received data with the programmed Xon character(s).
When a match occurs, the UART re-enables transmission
(see section 8.11.6).
For automatic in-band flow control, EFR[4] must be set.
The combinations of software receive flow control can be
selected by programming EFR[1:0] as follows:
logic [00] ⇒ In-band receive flow control is disabled.
logic [01] ⇒ Single character in-band receive flow control
enabled, recognizing Xon2 as the XON
character and Xoff2 as the XOFF character.
logic [10] ⇒ Single character in-band receive flow control
enabled, recognizing Xon1 as the Xon
character and Xoff1 and the Xoff character.
logic [11] ⇒ The behavior of the receive flow control
depends on the configuration of EFR[3:2].
Single-character in-band receive flow control
is enabled, accepting both Xon1 and Xon2 as
valid Xon characters and both Xoff1 and
Xoff2 as valid Xoff characters when EFR[3:2]
= 01 or 10. EFR[1:0] should not be set to 11
when EFR[3:2] is 00.
EFR[3:2]: In-band transmit flow control mode
When in-band transmit flow control is enabled, Xon/Xoff
characters are inserted into the data stream whenever the
RFL passes the upper trigger level and falls below the
lower trigger level respectively.
For automatic in-band flow control, EFR[4] must be set.
The combinations of software transmit flow control can
then be selected by programming EFR[3:2] as follows:
logic [00] ⇒
logic [01] ⇒
logic [10] ⇒
Logic[11] ⇒
In-band transmit flow control is disabled.
Single character in-band transmit flow
control enabled, using Xon2 as the Xon
character and Xoff2 as the Xoff character.
Single character in-band transmit flow
control enabled, using Xon1 as the Xon
character and Xoff1 as the Xoff character.
The value EFR[3:2] = 11 is reserved for
future use and should not be used
EFR[4]: Enhanced mode
logic 0 ⇒ Non-enhanced mode. Disables IER[7:4],
ISR[5:4], FiCR[5:4], MCR[7:5] and in-band flow
control. Whenever this bit is cleared, the
setting of other bits of EFR is ignored.
logic 1 ⇒ Enhanced mode. Enables the enhanced mode
functions. These functions include enabling
IER[7:4], FiCR[5:4], MCR[7:5]. For in-band
flow control the software driver must set this bit
first. If this bit is set, out-of-band flow control is
configured with EFR[7:6], otherwise out-of-
band flow control is compatible with 16C750.
EFR[5]: Enable special character detection
logic 0 ⇒ Special character detection is disabled.
logic 1 ⇒ While in Enhanced mode (EFR[4]=1), the
UART compares the incoming receiver data
with the XOFF2 value. Upon a correct match,
the received data will be transferred to the
RHR and a level 5 interrupt (XOFF or special
character) will be asserted if level 5 interrupts
are enabled (IER[5] set to 1).
EFR[6]: Enable automatic RTS flow control.
logic 0 ⇒ RTS flow control is disabled (default).
logic 1 ⇒ RTS flow control is enabled in enhanced mode
(i.e. EFR[4] = 1), where the RTS# pin is forced
inactive high if the RFL reaches the upper flow
control threshold. This is released when the
RFL drops below the lower threshold. The 650
and 950 software drivers should use this bit to
enable RTS flow control. The 750 compatible
driver uses MCR[5] to enable RTS flow control.
DS-0023 February 2007
External—Free Release
Page 53 of 74