OXCFU950_07 Datasheet, PDF (55/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
OXCFU950 DATA SHEET
8.10 Baud Rate Generation
8.10.1 General Operation
The UART contains a programmable baud rate generator
capable of taking the fixed 48-MHz clock input from the
OXCFU950 internal PLL and dividing it by any 16-bit
divisor number from 1 to 65535 written into the DLM (MSB)
and DLL (LSB) registers. In addition, a clock prescaler
register is provided which can further divide the clock by
values in the range 1.0 to 31.875 in steps of 0.125. A
further feature is the Times Clock Register (TCR) which
allows the sampling clock to be set to between 4 and 16.
These clock options allow for highly-flexible baud rate
generation. The actual transmitter and receiver baud rate is
calculated as follows:
BaudRate =
InputClock
SC * Divisor * prescaler
Where:
SC = Sample clock values defined in TCR[3:0]
Divisor = (256 x DLM ) + DLL
Prescaler = 1 when MCR[7] = 0 else:
= M + ( N / 8 ) where:
M
= CPR[7:3] (Integer part – 1 to 31)
N
= CPR[2:0] (Fractional part – 0.000 to 0.875 )
See Section 8.10.3 for a discussion of the clock prescaler
and times clock register.
After a hardware reset, the prescaler is bypassed (set to 1)
and TCR is set to 0x00 (i.e. SC = 16). Assuming this
default configuration, the following table gives the divisors
required to be programmed into the DLL and DLM registers
in order to obtain various standard baud rates:
DLM:DLL (Hex) Divisor Word
EA
60
6A
88
27
10
13
88
09
C4
04
E2
02
71
01
38
00
9C
00
68
00
4E
00
34
00
1A
Baud Rate (bps))
50
110
300
600
1,200
2,400
4,800
9,600
19,200
28,800
38,400
57,600
115,200
Table 26: Standard PC COM Port Baud Rate Divisors
8.10.2 Clock Prescaler Register—CPR
The CPR register is located at offset 0x01 of the ICR
The prescaler divides the system clock by any value in the
range of 1 to 31 7/8 in steps of 1/8. The divisor takes the
form M + N/8, where M is the 5-bit value defined in
CPR[7:3] and N is the 3-bit value defined in CPR[2:0].
The prescaler is by-passed and a prescaler value of 1 is
selected by default when MCR[7] = 0.
MCR[7] is reset to 0 after a hardware reset but may be
overwritten by software. Note: because access to MCR[7]
is restricted to enhanced mode only, EFR[4] should first be
set and then MCR[7] set or cleared as required.
If MCR[7] is set by software, the internal clock prescaler is
enabled.
Upon a hardware reset, CPR defaults to 0x20 (division-by-
4).
The flexible prescaler allows system designers to generate
popular baud rates using clocks that are not integer
multiples of the required rate. With the OXCFU950 fixed-
clock frequency, compatibility with existing 16C550
software drivers may be maintained with a minor software
patch to program the on-board prescaler to divide the high
frequency clock down to 1.8432 MHz.
Table 28 on the following page gives typical TCR, CPR and
Divisor values, which can be used to synthesize a range of
typical baud rates.
8.10.3 Times Clock Register—TCR
The TCR register is located at offset 0x02 of the ICR
The 16C550 and other compatible devices such as 16C654
and 16C750 use a 16 times (16x) over-sampling channel
clock. The 16x over-sampling clock means that the channel
clock runs at 16 times the selected serial bit rate. It limits
the highest baud rate to 1/16 of the system clock when
using a divisor latch value of unity. However, the 950
UART is designed to accept other multiplications of the bit
rate clock. It can use values from 4x to 16x clock as
programmed in the TCR as long as the clock (oscillator)
frequency error, stability and jitter are within reasonable
parameters. Upon hardware reset the TCR is reset to 0x00
which means that a 16x clock will be used, for compatibility
with the 16C550 and compatibles.
DS-0023 February 2007
External—Free Release
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