OXCFU950_07 Datasheet, PDF(46/74 Page) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

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OXCFU950_07 Datasheet, PDF (46/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

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OXFORD SEMICONDUCTOR, INC.

OXCFU950 DATA SHEET

This enables the host CPU to initiate a 32-bit access to the

word address of the replicated THR or RHR locations. This

is broken down into four separate byte-size accesses by

the system PC Card or CF controller. Because each byte is

individually accessed, the FIFO is shifted in the manner

previously described.

The DBURST register is provided to support this feature in

systems where only an 8-byte UART address space is

available. Writing 1 to bit 0 of the DBURST register enables

address locations 0x00 through 0x03 to be used in the

same way as locations 0x08 through 0x0B.

Although the number of accesses made to the OXCFU950

and maximum data throughput across the PC Card or CF

interface is increased.

8.4.2 FIFO Control RegisterâFiCR

FiCR[0]: Enable FIFO mode

logic 0 â Byte mode.

logic 1 â FIFO mode.

This bit should be enabled before setting the FIFO trigger

levels.

FiCR[1]: Flush RHR

logic 0 â No change.

logic 1 â Flushes the contents of the RHR

This is only operative in a FIFO mode. The RHR is flushed

automatically whenever changing between Byte mode and

a FIFO mode. This bit returns to zero after clearing the

FIFOs.

FiCR[2]: Flush THR

logic 0 â No change.

logic 1 â Flushes the contents of the THR in the same

manner as FiCR[1] does for the RHR.

DMA Transfer Signaling:

FiCR[3]: DMA signaling mode / Tx trigger level enable

logic 0 â DMA mode 0.

logic 1 â DMA mode 1.

DMA signals are not bonded out in the OXCFU950, so this

control only affects the transmitter trigger level in DMA

mode 0.

FiCR[5:4]: THR trigger level

Generally in 450, 550, extended 550 and 950 modes these

bits are unused (see section 8.1 for mode definition). In

650 mode they define the transmitter interrupt trigger levels

and in 750 mode FiCR[5] increases the FIFO size.

450, 550 and extended 550 modes:

The transmitter interrupt trigger levels are set to 1 and

FiCR[5:4] are ignored.

650 mode:

In 650 mode the transmitter interrupt trigger levels are set

to the following values:

FiCR[5:4]

Transmit Interrupt Trigger level

112

Table 20: Transmit Interrupt Trigger Levels

These levels only apply to enhanced mode and DMA mode

1 (FiCR[3] = 1), otherwise the trigger level is set to 1. A

transmitter empty interrupt will be generated (if enabled) if

the TFL falls below the trigger level.

750 Mode:

In 750 compatible non-enhanced (EFR[4]=0) mode,

transmitter trigger level is set to 1, FiCR[4] is unused and

FiCR[5] defines the FIFO depth as follows:

FiCR[5]=0 transmitter and receiver FIFO size is 16 bytes.

FiCR[5]=1 transmitter and receiver FIFO size is 128 bytes.

In non-enhanced mode FiCR[5] is only writable when

LCR[7] is set. Note: in enhanced mode, the FIFO size is

also increased to 128 bytes when FiCR[0] is set.

950 mode:

Setting ACR[5] to 1 enables arbitrary transmitter trigger

level setting using the TTL register (see section 8.11.4), so

FiCR[5:4] are ignored.

FiCR[7:6]: RHR trigger level

In 550, extended 550, 650 and 750 modes, the receiver

FIFO trigger levels are defined using FiCR[7:6]. The

interrupt trigger level and upper flow control trigger level

where appropriate are defined by L2 in the table below. L1

defines the lower flow control trigger level where

applicable. Separate upper and lower flow control trigger

levels introduce a hysteresis element in in-band and out-of-

band flow control (see section 8.9).

DS-0023 February 2007

ExternalâFree Release

Page 46 of 74

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