OXCFU950_07 Datasheet, PDF (58/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
ACR[1]: Transmitter disable
logic 0 ⇒ The transmitter is enabled, transmitting any
data in the THR.
logic 1 ⇒ The transmitter is disabled. Any data in the
THR is not transmitted but is held. However,
in-band flow control characters may still be
transmitted.
Changes to this bit are only recognized following the
completion of any data transmission pending.
ACR[2]: Enable automatic DSR flow control
logic 0 ⇒ Normal. The state of the DSR# line does not
affect the flow control.
logic 1 ⇒ Data transmission is prevented whenever the
DSR# pin is held inactive high.
This bit provides another automatic out-of-band flow control
facility using the DSR# line.
ACR[4:3]: DTR# line configuration
The DTR# pin is defined as follows:
logic [00] ⇒
logic [01] ⇒
logic [10] ⇒
logic [11] ⇒
DTR# is compatible with 16C450, 16C550,
16C654 and 16C750 (i.e. normal).
DTR# pin is used for out-of-band flow
control. It is forced inactive high if the RFL
reaches the upper flow control threshold.
DTR# line is re-activated when the RFL
drops below the lower threshold (see FCL &
FCH).
DTR# pin is configured to drive the active
low enable pin of an external RS485 buffer.
In this configuration the DTR# pin will be
forced low whenever the transmitter is not
empty (LSR[6]=0), otherwise DTR# pin is
high.
DTR# pin is configured to drive the active-
high enable pin of an external RS485 buffer.
In this configuration, the DTR# pin will be
forced high whenever the transmitter is not
empty (LSR[6]=0), otherwise DTR# pin is
low.
If the user sets ACR[4], the DTR# line is controlled by the
status of the transmitter empty bit of LCR. When ACR[4] is
set, ACR[3] is used to select active-high or active-low
enable signals. In half-duplex systems using RS485
protocol, this facility enables the DTR# line to directly
control the enable signal of external 3-state line driver
buffers. When the transmitter is empty the DTR# would go
inactive once the SOUT line returns to its idle marking
state.
OXCFU950 DATA SHEET
ACR[5]: 950 mode trigger levels enable
logic 0 ⇒ Interrupts and flow control trigger levels are
as described in FiCR register and are
compatible with 16C654/16C750 modes.
logic 1 ⇒ 950 specific enhanced interrupt and flow
control trigger levels defined by RTL, TTL,
FCL and FCH are enabled.
ACR[6]: ICR read enable
logic 0 ⇒ The LSR is readable.
logic 1 ⇒ The ICRs are readable.
Setting this bit maps the ICR set to the LSR location for
reads. During normal operation this bit should be cleared.
ACR[7]: Additional status enable
logic 0 ⇒ Access to the ASR, TFL and RFL registers
is disabled.
logic 1 ⇒ Access to the ASR, TFL and RFL registers
is enabled.
When ACR[7] is set, the MCR and LCR registers are no
longer readable but remain writable, and the TFL and RFL
registers replace them in the memory map for read
operations. The IER register is replaced by the ASR
register for all operations. The software driver may leave
this bit set during normal operation, since MCR, LCR and
IER do not generally need to be read.
8.11.4 Transmitter Trigger Level—TTL
The TTL register is located at offset 0x04 of the ICR
Whenever 950 trigger levels are enabled (ACR[5]=1), bits 4
and 5 of FiCR are ignored and an alternative arbitrary
transmitter interrupt trigger level can be defined in the TTL
register. This 7-bit value provides a fully programmable
transmitter interrupt trigger facility. In 950 mode, a priority
level 3 interrupt occurs indicating that the transmitter buffer
requires more characters when the interrupt is not masked
(IER[1]=1) and the transmitter FIFO level falls below the
value stored in the TTL register. The value 0 (0x00) has a
special meaning. In 950 mode when the user writes 0x00
to the TTL register, a level 3 interrupt only occurs when the
FIFO and the transmitter shift register are both empty and
the SOUT line is in the idle marking state. This feature is
particularly useful to report back the empty state of the
transmitter after its FIFO has been flushed away.
DS-0023 February 2007
External—Free Release
Page 58 of 74