OXCFU950_07 Datasheet, PDF (52/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
In this mode, the receiver and transmitter interrupts are
fully operational. The modem control interrupts are also
operational, but the interrupt sources are now the lower
four bits of the MCR instead of the four modem status
inputs. The interrupts are still controlled by the IER.
MCR[5]: Enable XON-Any in enhanced mode or enable
out-of-band flow control in non-enhanced mode
650/950 modes (enhanced mode):
logic 0 ⇒ XON-Any is disabled.
logic 1 ⇒ XON-Any is enabled.
In enhanced mode (EFR[4]=1), this bit enables the Xon-
Any operation. When Xon-Any is enabled, received data is
accepted as a valid Xon (see in-band flow control, section
8.9.3).
750 mode (non-enhanced mode):
logic 0 ⇒ CTS/RTS flow control disabled.
logic 1 ⇒ CTS/RTS flow control enabled.
In non-enhanced mode, this bit enables the CTS/RTS out-
of-band flow control.
MCR[6]: IrDA mode
logic 0 ⇒ Standard serial receiver & transmitter data
format.
logic 1 ⇒ Data is transmitted & received in IrDA format.
This function is only available in enhanced mode. It
requires a 16x clock to function correctly.
MCR[7]: Baud rate prescaler select
logic 0 ⇒ Normal (divide by 1) baud rate generator
prescaler selected.
logic 1 ⇒ Divide-by-M N/8 baud rate generator prescaler
selected.
8.8 Other Standard Registers
8.8.1 Divisor Latch Registers—DLL & DLM
The divisor latch registers are used to program the baud
rate divisor. This is a value between 1 and 65535 by which
the input clock is divided by in order to generate serial
baud rates. After See section 8.10 for full details.
OXCFU950 DATA SHEET
Where M & N are programmed in CPR (ICR offset 0x01).
After a hardware reset, CPR defaults to 0x20 (divide-by-4)
and MCR[7] is reset to 0. User writes to this flag only take
effect in enhanced mode. See section 8.9.1.
8.7.2 Modem Status Register—MSR
MSR[0]: Delta CTS#
Indicates that the CTS# input has changed since the last
time the MSR was read.
MSR[1]: Delta DSR#
Indicates that the DSR# input has changed since the last
time the MSR was read.
MSR[2]: Trailing edge RI#
Indicates that the RI# input has changed from low to high
since the last time the MSR was read.
MSR[3]: Delta DCD#
Indicates that the DCD# input has changed since the last
time the MSR was read.
MSR[4]: CTS
This bit is the complement of the CTS# input. It is
equivalent to RTS (MCR[1]) during internal loop-back
mode.
MSR[5]: DSR
This bit is the complement of the DSR# input. It is
equivalent to DTR (MCR[0]) during internal loop-back
mode.
MSR[6]: RI
This bit is the complement of the RI# input. In internal loop-
back mode it is equivalent to the internal OUT1.
MSR[7]: DCD
This bit is the complement of the DCD# input. In internal
loop-back mode it is equivalent to the internal OUT2.
8.8.2 Scratch Pad Register—SPR
The scratch pad register does not affect operation of the
rest of the UART in any way and can be used for
temporary data storage. The register may also be used to
define an offset value to access the registers in the
Indexed Control Register set. For more information on
Indexed Control registers see Table 17 and section 8.11.
DS-0023 February 2007
External—Free Release
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