OXCFU950_07 Datasheet, PDF (41/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
OXCFU950 DATA SHEET
8.2 Register Description Tables
The UART registers are accessible from the host machine I/O space. In order to support legacy software, selection of the
registers is also dependent on the state of the LCR and ACR:
1. LCR[7]=1 enables the divider latch registers DLL and DLM.
2. LCR specifies the data format used for both transmitter and receiver. Writing 0xBF (an unused format) to LCR enables
access to the 650 compatible register set. Writing this value will set LCR[7] but leaves LCR[6:0] unchanged. Therefore, the
data format of the transmitter and receiver data is not affected. Write the desired LCR value to exit from this selection.
3. ACR[7]=1 enables access to the 950 specific registers.
4. ACR[6]=1 enables access to the Indexed Control Register set (ICR) registers as described on page 43.
Register Address⁰ R/
Name
W
THR ¹
0x00
W
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3 Bit 2
Data to be transmitted
Bit 1
Bit 0
RHR ¹
0x00
R
Data received
IER ^1,2
650/950
Mode
550/750
Mode
CTS
RTS Special
0x01
interrupt interrupt
R/W ^mask
mask
Char.
Detect
Modem Rx Stat THRE
Unused interrupt interrupt interrupt
RxRDY
interrupt
Unused
mask
mask
mask
mask
FiCR ³
650 mode
750 mode
0x02
W
950 mode
RHR Trigger
Level
RHR Trigger
Level
THR Trigger
Level
FIFO
Size
Unused
Unused
DMA
Mode /
Tx
Trigger
Enable
Flush
THR
Flush
RHR
Enable
FIFO
ISR ³
0x02
R
FIFOs
enabled
Interrupt priority
(Enhanced mode)
Interrupt priority
(All modes)
Interrupt
pending
LCR ⁴
0x03
Divisor
R/W latch
access
Tx
break
Force
parity
Odd /
even
parity
Parity
enable
Number
of stop
bits
Data length
MCR ^3,4
550/750
Mode
0x04
R/W
Unused
CTS &
RTS Internal
Flow
Control
Loop
Back
OUT2
(Int En)
OUT1
RTS
DTR
650/950
Mode
Baud
prescale
IrDA
mode
Enable
XON-Any
LSR ^3,5
Normal
0x05
9-bit data
mode
Data
Error
Tx Empty
THR
Empty
Rx
Break
Framing
Error
Parity
Error
Overrun
Error
R
9^th Rx
data bit
MSR ³
0x06
R
DCD
RI
DSR
CTS
Delta Trailing Delta
DCD RI edge DSR
SPR ³
Normal
9-bit data
mode
0x07
R/W
Temporary data storage register and
Indexed control register offset value bits
Unused
Additional Standard Registers – These registers require divisor latch access bit (LCR[7]) to be set to 1.
RxRDY
Delta
CTS
9^th Tx
data bit
DLL
0x00
R/W
Divisor latch bits [7:0] (Least significant byte)
DLM
0x01
R/W
Divisor latch bits [15:8] (Most significant byte)
Table 13: Standard 550-Compatible Registers
DS-0023 February 2007
External—Free Release
Page 41 of 74