OXCFU950_07 Datasheet, PDF (22/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
6.6.3 MIO Interrupts
To enable one or more MIO interrupts, the appropriate
bit(s) in the MIO interrupt enable register (an LCR at offset
0x13) must be set to ‘1’ by the host system. Bit 0
corresponds to the MIO[0] interrupt enable, bit 1
corresponds to MIO[1] interrupt enable, bit 2 corresponds
to MIO[2] interrupt enable and bit 3 corresponds to MIO[3]
interrupt enable. When an MIO interrupt is asserted, the
Intr field in the UART CSR is set to ‘1’
6.6.4 UART Interrupts
To enable the UART interrupt, set bit 0 (the UART interrupt
enable bit in the UART interrupt enable register, which is
an LCR register at offset 0x15) to ‘1’. When a UART
interrupt is asserted, the Intr field within the UART CSR is
set to ‘1’.
6.6.5 USB Interrupts
The OXCFU950 supports two forms of USB interrupt: the
standard OHCI interrupt (standard IRQ) and a faster
interrupt. Oxford Semiconductor USB host driver software
uses the faster interrupt (fast IRQ) to improve system
performance.,
USB Standard IRQ
To enable the USB interrupt, set bit 0 (the USB Host
interrupt enable bit in the USB interrupt enable register, an
LCR register at offset 0x14) to ‘1’. When a USB interrupt is
asserted the Intr field within the USB CSR is set to ‘1’.
USB Fast IRQ
To enable the fast USB IRQ, set bit 1, the USB host fast
enable bit in the USB interrupt enable register (an LCR
register at offset 0x14) to ‘1’.
6.6.6 UART/USB Test Interrupts
There is a test facility for the host system to initiate UART
and USB interrupts by writing to the UART/USB Interrupt
Test Register at offset address 0x12. To force a function 0
UART interrupt, set bit 0 of the UART/USB Interrupt Test
Register to ‘1’. To force a function 1 USB interrupt, set bit 1
of the UART/USB Interrupt Test Register to ‘1’.
OXCFU950 DATA SHEET
6.6.7 Configuration & Status Register Interrupt
Request/Acknowledge
Intr Field
The Intr field (bit 1 of the CSR) reports whether the function
is requesting interrupt servicing and may be used to
acknowledge that the host system is ready to process
another interrupt request from the PC Card.
The function sets this field to ‘1’ to request interrupt
service. ‘0’ signifies that it is not requesting interrupt
service.
Writes to the Intr field in the CSR are ignored when the
IntrAck field of both CSRs on the PC Card are reset to
zero. If the host system writes a ‘0’ to this field in any CSR
on the PC Card when the IntAck field of any CSR is set to
‘1’ and either function on the PC Card is requesting
interrupt servicing, the PC Card must create an additional
interrupt notification to the host system.
IntrAck Field
The interrupt acknowledge field (IntrAck, bit 0 of the CSR)
changes the response characteristics of the Intr field. This
field is used to enable a hardware/software protocol that
permits the IREQ# signal to be shared by the two
functions.
If the IntrAck bit for both function CSRs is set to ‘0’, writes
to the Intr field are ignored. If the IntAck bit for either
function is set to ‘1’:
• The host system must acknowledge it is ready to
receive additional interrupts from the PC Card by
writing ‘0’ to the Intr field of either function CSR after
the host system has completed an entire interrupt
processing cycle.
• The PC Card creates an additional interrupt
notification to the host system when the host system
writes a ‘0’ to the Intr bit to either function CSR and
either function on the PC Card enabled for interrupt
reporting and sharing is requesting interrupt service.
DS-0023 February 2007
External—Free Release
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