OXCFU950_07 Datasheet, PDF (42/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
OXCFU950 DATA SHEET
Register Address R/W Bit 7 Bit 6 Bit 5
Name
To access these registers LCR must be set to 0xBF
EFR
010
R/W CTS
RTS Special
flow
Flow
char
control control detect
XON1
100
R/W
9-bit mode
XON2
101
R/W
9-bit mode
XOFF1
110
R/W
9-bit mode
XOFF2
111
R/W
9-bit mode
Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
Enhanced
mode
In-band flow control mode
XON Character 1
Special character 1
XON Character 2
Special Character 2
XOFF Character 1
Special character 3
XOFF Character 2
Special character 4
Table 14: 650 Compatible Registers
Register
Name
ASR ^1,6,7
Address
001
R/W
R/W ⁷
RFL ^{6, 10}
011
R
Bit 7
Tx
Idle
Bit 6
FIFO
size
Bit 5 Bit 4 Bit 3 Bit 2
‘0’
Special DTR
RTS
Char
Detect
Number of characters in the receiver FIFO
Bit 1
Remote
Tx
Disabled
Bit 0
Tx
Disabled
TFL ^{3,6, 10}
100
R
Number of characters in the transmitter FIFO
ICR ^3,8,9
101
R/W
Data read/written depends on the value written to the SPR prior to
the access of this register (see Table 17)
Table 15: 950 Specific Registers
Register Address⁰ R/ Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
W
32-bit¹¹
FIFO
Access
registers
0x08¹¹
to
0x0B
On any write to these registers a byte will be written to the TX FIFO. Writing any of these locations is
W
functionally the same as writing to THR (Address offset 0x00).
R
On any read of these registers a byte will be returned from the RX FIFO. Reading any of these
locations is functionally the same as reading RHR (Address offset 0x00).
0x0C
This location is not assigned to the UART
TFL¹⁰
0x0D
R
Returns the Tx FIFO fill level.
RFL¹⁰
0x0E
R
Returns the Rx FIFO fill level.
GDS¹⁰
0x0F
R
Table 16: OXCFU950 Specific Registers
Good
Data
Status
DS-0023 February 2007
External—Free Release
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