OXCFU950_07 Datasheet, PDF (4/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
OXCFU950 DATA SHEET
6.7.5 I/O BASE ADDRESS REGISTER—IOBA (OFFSET 0X0A & 0X0C) ............................................................................ 26
6.8 CARD INFORMATION STRUCTURE............................................................................................................................... 26
6.8.1 FIXED DEFAULT CIS IMAGE....................................................................................................................................... 26
6.8.2 STANDARD PRE-PROGRAMMED CIS IMAGE........................................................................................................... 29
6.8.3 EXAMPLE USB SINGLE FUNCTION CIS IMAGE........................................................................................................ 31
6.8.4 EXAMPLE UART SINGLE FUNCTION CIS IMAGE ..................................................................................................... 33
7 USB HOST CONTROLLER ................................................................................................................. 35
7.1 WRITING TO AN OHCI REGISTER IN THE EMBEDDED USB HOST CONTROLLER.................................................. 37
7.2 READING FROM AN OHCI REGISTER IN THE EMBEDDED USB HOST CONTROLLER ........................................... 37
7.3 WRITING TO THE USB MEMORY ................................................................................................................................... 37
7.4 READING FROM USB MEMORY..................................................................................................................................... 38
7.5 ACCESSING USB MEMORY VIA COMMON MEMORY ACCESS.................................................................................. 38
7.6 USB HOST CONTROLLER OVERVIEW.......................................................................................................................... 38
8 UART INTERFACE.............................................................................................................................. 39
8.1 MODE SELECTION .......................................................................................................................................................... 39
8.1.1 450 MODE..................................................................................................................................................................... 39
8.1.2 550 MODE..................................................................................................................................................................... 39
8.1.3 750 MODE..................................................................................................................................................................... 39
8.1.4 650 MODE..................................................................................................................................................................... 39
8.1.5 950 MODE..................................................................................................................................................................... 40
8.2 REGISTER DESCRIPTION TABLES ............................................................................................................................... 41
8.3 RESET CONFIGURATION ............................................................................................................................................... 45
8.3.1 HOST RESET ............................................................................................................................................................... 45
8.3.2 SOFTWARE RESET ..................................................................................................................................................... 45
8.4 TRANSMITTER & RECEIVER FIFOS .............................................................................................................................. 45
8.4.1 4-BYTE ACCESS TO THR & RHR ............................................................................................................................... 45
8.4.2 FIFO CONTROL REGISTER—FICR ............................................................................................................................ 46
8.5 LINE CONTROL & STATUS............................................................................................................................................. 47
8.5.1 FALSE START BIT DETECTION.................................................................................................................................. 47
8.5.2 LINE CONTROL REGISTER—LCR.............................................................................................................................. 47
8.5.3 LINE STATUS REGISTER—LSR ................................................................................................................................. 48
8.6 UART INTERRUPTS......................................................................................................................................................... 49
8.6.1 INTERRUPT ENABLE REGISTER—IER...................................................................................................................... 49
8.6.2 INTERRUPT STATUS REGISTER—ISR...................................................................................................................... 50
8.6.3 INTERRUPT DESCRIPTION ........................................................................................................................................ 50
8.6.4 UART POWER SAVING ............................................................................................................................................... 51
8.7 MODEM INTERFACE ....................................................................................................................................................... 51
8.7.1 MODEM CONTROL REGISTER—MCR....................................................................................................................... 51
8.7.2 MODEM STATUS REGISTER—MSR .......................................................................................................................... 52
8.8 OTHER STANDARD REGISTERS ................................................................................................................................... 52
8.8.1 DIVISOR LATCH REGISTERS—DLL & DLM............................................................................................................... 52
8.8.2 SCRATCH PAD REGISTER—SPR .............................................................................................................................. 52
8.9 AUTOMATIC FLOW CONTROL....................................................................................................................................... 53
8.9.1 ENHANCED FEATURES REGISTER—EFR................................................................................................................ 53
8.9.2 SPECIAL CHARACTER DETECTION .......................................................................................................................... 54
8.9.3 AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 54
8.9.4 AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 54
8.10 BAUD RATE GENERATION............................................................................................................................................. 55
8.10.1 GENERAL OPERATION ............................................................................................................................................... 55
8.10.2 CLOCK PRESCALER REGISTER—CPR..................................................................................................................... 55
8.10.3 TIMES CLOCK REGISTER—TCR................................................................................................................................ 55
8.10.4 ALTERNATIVE BAUD RATE CONTROL REGISTERS................................................................................................ 56
8.11 ADDITIONAL FEATURES ................................................................................................................................................ 57
8.11.1 ADDITIONAL STATUS REGISTER—ASR ................................................................................................................... 57
8.11.2 FIFO FILL LEVELS—TFL & RFL .................................................................................................................................. 57
DS-0023 February 2007
External—Free Release
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