OXCFU950_07 Datasheet, PDF (36/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
OXCFU950 DATA SHEET
Offset from I/O
base address
(byte-based)
0x20
Name
Register Address
0x23
Register Control
0x24
Register Write Data 0
0x25
Register Write Data 1
0x26
Register Write Data 2
0x27
Register Write Data 3
0x28
Register Read Data 0
0x29
Register Read Data 1
0x2A
Register Read Data 2
0x2B
Register Read Data 3
0x30
Memory Address 0
0x31
Memory Address 1
0x33
Memory Control
0x34
Memory Write Data 0
0x35
Memory Write Data 1
0x36
Memory Write Data 2
0x37
Memory Write Data 3
0x38
Memory Read Data 0
0x39
Memory Read Data 1
0x3A
Memory Read Data 2
0x3B
Memory Read Data 3
0x3C
Memory Page Select
0x3D
USB Coverage Reg 1
Description
Address of USB Register to be indirectly read/written. (Quadlet address, i.e. 1, 2, 3 etc, not 0,
4, 8…)
7: if ‘1’ then USB host controller is out of reset and ready for operation.
7: if ‘0’ then USB host controller is in reset and not yet ready for operation.
6: reserved
5: reserved
4: reserved
3: reserved
2: reserved
1: if ‘1’ then last write operation has been completed.
0: if ‘1’ then it is safe to read contents of Register Read Data 0-3”
Bits 7 down to 0 of 32-bit data to be written to the USB registers.
Bits 15 down to 8 of 32-bit data to be written to the USB registers.
Bits 23 down to 16 of 32-bit data to be written to the USB registers.
Bits 31 down to 24 of 32-bit data to be written to the USB registers.
Bits 7 down to 0 of 32-bit data to be read from the USB registers.
Bits 15 down to 8 of 32-bit data to be read from the USB registers.
Bits 23 down to 16 of 32-bit data to be read from the USB registers.
Bits 31 down to 24 of 32-bit data to be read from the USB registers.
Address of memory location to be indirectly read/written (bits 7 down to 0).
Address of memory location to be indirectly read/written (bits 15 down to 8).
7: Reserved
6: Reserved
5: Reserved
4: Reserved
3: Reserved
2: Reserved
1: if ‘1’ then last write operation has been completed.
0: if ‘1’ then it is safe to read contents of Memory Read Data 0-3.
Bits 7 down to 0 of 32-bit data to be written to the USB memory.
Bits 15 down to 8 of 32-bit data to be written to the USB memory.
Bits 23 down to 16 of 32-bit data to be written to the USB memory.
Bits 31 down to 24 of 32-bit data to be written to the USB memory.
Bits 7 down to 0 of 32-bit data to be read from the USB memory.
Bits 15 down to 8 of 32-bit data to be read from the USB memory.
Bits 23 down to 16 of 32-bit data to be read from the USB memory.
Bits 31 down to 24 of 32-bit data to be read from the USB memory.
1:0 = “11” Page 3 (locations 6144-8191) selected.
1:0 = “10” Page 2 (locations 4096-6143) selected.
1:0 = “01” Page 1 (locations 2048-4095) selected.
1:0 = “00” Page 0 (locations 0-2047) selected.
Bits 7 to 1 are readable and, if set, give the following information:
7: Common memory read has occurred since last reset.
6: Common memory write has occurred since last reset.
5: IAR RAM read has occurred since last reset.
4: HCI read has occurred since last reset.
3: HCI write (with at least one byte lane disabled) has occurred since last reset.
2: IAR RAM Write has occurred since last reset.
1: HCI write (no byte lanes disabled) has occurred since last reset.
Bit 0 must be set to enable the USB coverage registers.
DS-0023 February 2007
External—Free Release
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