OXCFU950_07 Datasheet, PDF (50/74 Pages) Oxford Semiconductor – USB/UART multi-function 16-bit PC Card device

OXFORD SEMICONDUCTOR, INC.
OXCFU950 DATA SHEET
8.6.2 Interrupt Status Register—ISR
The source of the highest priority interrupt pending is
indicated by the contents of the interrupt status register
ISR. There are nine sources of interrupt at six levels of
priority (1 is the highest) as tabulated below:
Level
Interrupt source
ISR[5:0]
see note 3
-
No interrupt pending ¹
000001
1
Receiver status error or
000110
Address-bit detected in 9-bit mode
2a
Receiver data available
000100
2b
Receiver time-out
001100
3
Transmitter THR empty
000010
4
Modem status change
000000
5 ² In-band flow control XOFF or Special 010000
character (XOFF2) or Special
character 1, 2, 3 or 4 or
bit 9 set in 9-bit mode
6²
CTS or RTS change of state
100000
Table 25: Interrupt Status Identification Codes
Note1:
Note2:
Note3:
8.6.3
ISR[0] indicates whether any interrupts are pending.
Interrupts of priority levels 5 and 6 cannot occur unless
the UART is in Enhanced mode.
ISR[5] is only used in 650 & 950 modes. In 750 mode, it
is 0 when FIFO size is 16 and 1 when FIFO size is 128.
In all other modes it is permanently set to 0.
Interrupt Description
Level 1:
Receiver status error interrupt (ISR[5:0]=’000110’):
Normal (non-9-bit) mode:
This interrupt is active whenever any of LSR[1], LSR[2],
LSR[3] or LSR[4] are set. These flags are cleared following
a read of the LSR. This interrupt is masked with IER[2].
9-bit mode:
This interrupt is active whenever any of LSR[1], LSR[2],
LSR[3] or LSR[4] are set. The receiver error interrupt due
to LSR[1], LSR[3] and LSR[4] is masked with IER[3]. The
‘address-bit’ received interrupt is masked with NMR[1]. The
software driver can differentiate between receiver status
error and received address-bit (9^th data bit) interrupt by
examining LSR[1] and LSR[7]. In 9-bit mode LSR[7] is only
set when LSR[3] or LSR[4] is set and it is not affected by
LSR[2] (i.e. 9^th data bit).
Level 2a:
Receiver data available interrupt (ISR[5:0]=’000100’):
This interrupt is active whenever the receiver FIFO level is
above the interrupt trigger level.
Level 2b:
Receiver time-out interrupt (ISR[5:0]=’001100’):
A receiver time-out event, which may cause an interrupt,
will occur when all of the following conditions are true:
• The UART is in a FIFO mode
• There is data in the RHR.
• There has been no read of the RHR for a period of
time greater than the time-out period.
• There has been no new data received and written into
the RHR for a period of time greater than the time-out
period. The time-out period is four times the character
period (including start and stop bits) measured from
the centre of the first stop bit of the last data item
received.
Reading the first data item in RHR clears this interrupt.
Level 3:
Transmitter empty interrupt (ISR[5:0]=’000010’):
This interrupt is set when the transmit FIFO level falls
below the trigger level. It is cleared on an ISR read of a
level 3 interrupt or by writing more data to the THR so that
the trigger level is exceeded. Note that when 950 mode
trigger levels are enabled (ACR[5]=1) and the transmitter
trigger level of zero is selected (TTL=0x00), a transmitter
empty interrupt is only asserted when both the transmitter
FIFO and transmitter shift register are empty and the
SOUT line has returned to idle marking state.
Level 4:
Modem change interrupt (ISR[5:0]=’000000’):
This interrupt is set by a modem change flag (MSR[0],
MSR[1], MSR[2] or MSR[3]) becoming active due to
changes in the input modem lines. This interrupt is cleared
following a read of the MSR.
Level 5:
Receiver in-band flow control (Xoff) detect interrupt,
Receiver special character (Xoff2) detect interrupt,
Receiver special character 1, 2, 3 or 4 interrupt or
9^th Bit set interrupt in 9-bit mode (ISR[5:0]=010000):
A level 5 interrupt can only occur in enhanced-mode when
any of the following conditions are met:
• A valid Xoff character is received while in-band flow
control is enabled.
• A received character matches Xoff2 while special
character detection is enabled.
• A received character matches special character 1, 2, 3
or 4 in 9-bit mode (see section 8.11.8).
It is cleared on an ISR read of a level 5 interrupt.
DS-0023 February 2007
External—Free Release
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